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2023年12月8日发(作者：运馨)

K9F2G08U0C

FLASH MEMORY

K9F2G08X0CINFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALLINFORMATION IN THIS DOCUMENT IS PROVIDEDON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.1. For updates or additional information about Samsung products, contact your nearest Samsung office.2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similarapplications where Product failure could result in loss of life or personal or physical harm, or any military ordefense application, or any governmental procurement to which special terms or provisions may apply.

* Samsung Electronics reserves the right to change products or specification without notice.

Samsung Confidential1K9F2G08U0C

FLASH MEMORYDocument Title256M x 8 Bit NAND Flash MemoryRevision HistoryRevision No0.00.1History1. Initial issue1. DC Parameter is chagned

2. Typo is modifiedDraft DateAug. 12, 2009Dec. 9, 2009RemarkAdvanceAdvance

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the rightto change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you haveany questions, please contact the SAMSUNG branch office near your g Confidential2K9F2G08U0C

FLASH MEMORY1.0 Introduction1.1 PRODUCT LISTPart NumberK9F2G08U0C-SK9F2G08U0C-HVcc Range2.7 ~ 3.6v2.7 ~ 3.6vOrganizationx8x8PKG TypeTSOP163 FBGA1.2 FEATURES• Voltage Supply

- 3.3V device(K9F2G08U0C): 2.70V ~ 3.60V• Organization - Memory Cell Array : (256M + 8M) x 8bit - Data Register : (2K + 64) x 8bit

• Automatic Program and Erase - Page Program : (2K + 64)Byte - Block Erase : (128K + 4K)Byte• Page Read Operation - Page Size : (2K + 64)Byte - Random Read : 35µs(Max.) - Serial Access : 30ns(Min.)

• Fast Write Cycle Time - Page Program time : 250µs(Typ.) - Block Erase Time : 2ms(Typ.)• Command/Address/Data Multiplexed I/O Port• Hardware Data Protection - Program/Erase Lockout During Power Transitions• Reliable CMOS Floating-Gate Technology -Endurance & Data Retention : Refor to the gualification report -ECC regnirement : 1 bit / 528bytes• Command Driven Operation• Unique ID for Copyright Protection• Package :

- K9F2G08U0C-SCB0/SIB0 : Pb-FREE PACKAGE 48 - Pin TSOP I (12 x 20 / 0.5 mm pitch) - K9F2G08U0C-HCB0/HIB0 : Pb-FREE PACKAGE 63 - ball FBGA (9 x 11 / 0.8 mm pitch)1.3 GENERAL DESCRIPTIONOffered in 256Mx8bit, the K9F2G08X0C is a 2G-bit NAND Flash Memory with spare 64M-bit. Its NAND cell provides the most cost-effective solution for the solid state application market. A program operation can be performed in typical 250µs on the (2K+64)Byte

page and an erase operation can be performed in typical 2ms on a (128K+4K)Byte block. Data in the data register can be read out at

30ns cycle time per Byte. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip

write controller automates all program and erase functions including pulse repetition, where required, and internal verification and

margining of data. Even the write-intensive systems can take advantage of the K9F2G08X0C′s extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9F2G08X0C is an optimum solu-tion for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.

Samsung Confidential3K9F2G08U0C1.4

PIN CONFIGURATION (TSOP1)K9F2G08X0C-HCB0//B .C17/O7I/O6I/O5I//O3I/O2I/O1I/.C

FLASH MEMORY48-pin TSOP1Standard Type12mm x 20mmPACKAGE DIMENSIONS48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)48 - TSOP1 - 1220F

Unit :mm/Inch0.10

MAX0.004

20.00±0.200.787±0.0080.008-0.001+0.003+0.070.20-0.03#1#48(0.25)0.01012.400.488MAX0.500.0197#24#251.00±0.050.039±0.0020.050.002MIN0.250.010TYP0.1250.0350~8°0.45~0.750.018~0.030(0.50)0.020Samsung Confidential40.005-0.001+0.00318.40±0.100.724±0.004+0.0751.200.047MAX12.000.472K9F2G08U0C1.5 PIN CONFIGURATION (FBGA)K9F2G08X0C-HCB0/HIB0Top View 1 .C

FLASH .C/WPNCNCNCNCNCNCVssALE/RENCNCNCI/O0I/O1I/O2VssCLENCNCNCNCNC/CENCNCNCNCNC/WENCNCNCR/BNCNCNCDEFGHNC NCNCVccI/O7VssVccQI/O5I/O6I/O3I/ng Confidential5K9F2G08U0C1.5.1 PACKAGE DIMENSIONS

FLASH MEMORY63-Ball FBGA (measured in millimeters)Top ViewBottom View9.00±0.100.80 x 9= 7.20

0.80 x 5= 4.00

9.00±0.10(Datum A)A60.8054321B#A1AB0.80

x11=

8.80

0.80

x7=

5.60

2.00(Datum B)CDE0.8011.00±0.102.80FGH63-∅0.45±0.05∅0.20

A B

Side View9.00±0.100.10MAX0.45±0.05Samsung Confidential61.00(Max.)0.25(Min.)11.00±0.10K9F2G08U0C1.6

PIN DESCRIPTIONPin NameI/O0 ~ I/O7Pin Function

FLASH MEMORYDATA INPUTS/OUTPUTS

The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z when the chip is deselected or when the outputs are disabled.

COMMAND LATCH ENABLEThe CLE input controls the activating path for commands sent to the command register. When active high,

commands are latched into the command register through the I/O ports on the rising edge of the WE S LATCH ENABLEThe ALE input controls the activating path for address to the internal address registers. Addresses are

latched on the rising edge of WE with ALE ENABLEThe CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and

the device does not return to standby mode in program or erase ENABLEThe RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid

tREA after the falling edge of RE which also increments the internal column address counter by ENABLEThe WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of

the WE PROTECTThe WP pin provides inadvertent program/erase protection during power transitions. The internal high volt-age generator is reset when the WP pin is active /BUSY OUTPUTThe R/B output indicates the status of the device operation. When low, it indicates that a program, erase or

random read operation is in process and returns to high state upon completion. It is an open drain output and

does not float to high-z condition when the chip is deselected or when outputs are CC is the power supply for device.

GROUNDNO CONNECTIONLead is not internally CEREWEWPR/ : Connect all VCC and VSS pins of each device to common power supply outputs. Do not leave VCC or VSS g Confidential7K9F2G08U0C2.0 Product Introduction

FLASH MEMORYNAND Flash Memory has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system

upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through

I/O's by bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address

Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus

cycle. For example, Reset Command, Status Read Command, etc. require just one cycle bus. Some other commands, like page read

and block erase and page program, require two cycles: one cycle for setup and the other cycle for execution.. Page Read and Page

Program need the same five address cycles following the required command input. In Block Erase operation, however, only the three

row address cycles are used. Device operations are selected by writing specific commands into the command register. Table 1

defines the specific commands of the 1. Command Sets

FunctionRead for Copy BackRead IDResetPage ProgramCopy-Back ProgramTwo-Plane Page Program(2)Block EraseRandom Data Input(1)Random Data Output(1)Read StatusRead Status 21st Cycle00h90hFFh80h85h80h---11h60h85h05h70hF1h2nd Cycle30h35h--10h10h81h---10hD0h-E0h--OOOAcceptable Command during BusyRead 00hNOTE : 1. Random Data Input/Output can be executed in a page. 2. Any command between 11h and 81h is prohibited except 70h/F1h and n :

Any undefined command inputs are prohibited except for above command set of Table 1.

Samsung Confidential8K9F2G08U0C2.1

ABSOLUTE MAXIMUM RATINGSParameterVoltage on any pin relative to VSSSymbolVCCVINVI/OTemperature Under

BiasStorage TemperatureShort Circuit CurrentK9F2G08X0C-XCB0K9F2G08X0C-XIB0K9F2G08X0C-XCB0K9F2G08X0C-XIB0TBIASTSTGIOS

FLASH MEMORYRating-0.6 to +4.6-0.6 to +4.6-0.6 to Vcc + 0.3 (< 4.6V)-10 to +125-40 to +125-65 to +1505°C°CmAUnitVNOTE :

1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.

Maximum DC voltage on input/output pins is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.2.2 RECOMMENDED OPERATING CONDITIONS(Voltage reference to GND, K9F2G08X0C-XCB0

:TA=0 to 70°C, K9F2G08X0C-XIB0:TA=-40 to 85°C)ParameterSupply VoltageSupply VoltageSymbolVCCVSS3.3VMin2.70Typ.3.30Max3.60UnitVV2.3

DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise

ParameterPage Read with Serial

AccessProgramEraseStand-by Current(TTL)Stand-by Current(CMOS)Input Leakage CurrentOutput Leakage CurrentInput High VoltageInput Low Voltage, All inputsOutput High Voltage LevelOutput Low Voltage LevelOutput Low Current(R/B)SymbolICC1ICC2ICC3ISB1ISB2ILIILOVIH(1)VIL(1)VOHVOLIOL(R/B)Test ConditionstRC=30nsCE=VIL,

IOUT=0mA--CE=VIH, WP=0V/VCCCE=VCC-0.2, WP=0V/VCCVIN=0 to Vcc(max)VOUT=0 to Vcc(max)--K9F2G08B0C: IOH=-100µAK9F2G08U0C: IOH=-400µAK9F2G08B0C: IOL=100µAK9F2G08U0C: IOL=2.1mAK9F2G08B0C: VOL=0.1VK9F2G08U0C: VOL=0.4V----0.8xVcc-0.32.4-8-10------10150±10±10Vcc+0.30.2xVcc-0.4-mAVµA-2035mA3.3VMinTypMaxUnitOperating

Currentnoted.)NOTE : 1. VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less. 2. Typical value is measured at Vcc= 3.3V, TA=25°C. Not 100% tested.

Samsung Confidential9K9F2G08U0C2.4

VALID BLOCKParameterK9F2G08X0CSymbolNVBMin2,008Typ.-

FLASH MEMORYMax2,048UnitBlocksNOTE :

1. The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks ispresented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or pro-gram factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks.2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/528Byte ECC.3. The number of valid block is on the basis of single plane operations, and this may be decreased with two plane operations.

2.5 AC TEST CONDITION

(K9F2G08X0C-XCB0 :TA=0 to 70°C, K9F2G08X0C-XIB0:TA=-40 to 85°C, K9F2G08U0C: Vcc=2.7V~3.6V unless otherwise noted)ParameterInput Pulse LevelsInput Rise and Fall TimesInput and Output Timing LevelsOutput LoadK9F2G08X0C0V to Vcc5nsVcc/21 TTL GATE and CL=50pF2.6

CAPACITANCE(TA=25°C, VCC= 3.3V, f=1.0MHz)ItemInput/Output CapacitanceInput CapacitanceSymbolCI/OCINTest ConditionVIL=0VVIN=0VMin--Max1010UnitpFpFNOTE : Capacitance is periodically sampled and not 100% tested.2.7

MODE SELECTIONCLEHLHLLLXXXXXALELHLHLLXXXX(1)XCELLLLLLXXXXHHXXXXXHXXXXWEREHHHHHWPXXHHHXXHHL0V/VCC(2)Read ModeWrite Mode Data InputDataOutputDuringRead(Busy)DuringProgram(Busy)DuringErase(Busy) Write Protect Stand-byMode Command Input Address Input(5clock) Command Input Address Input(5clock)NOTE : 1. X can be VIL or VIH.2. WP should be biased to CMOS high or CMOS low for g Confidential10K9F2G08U0C2.8

Program / Erase CharacteristicsParameterProgram Time

Number of Partial Program Cycles

Block Erase TimeNOTE :1. Typical value is measured at Vcc=3.3V, TA=25°C. Not 100% tested.

FLASH MEMORYSymboltPROGNoptBERSMin---Typ250-2Max750410Unitµscyclesms2. Typical program time is defined as the time within which more than 50% of the whole pages are programmed at 3.3V Vcc and 25°C temperature.2.9

AC Timing Characteristics for Command / Address / Data InputParameterCLE Setup TimeCLE Hold TimeCE Setup TimeCE Hold TimeWE Pulse WidthALE Setup TimeALE Hold TimeData Setup TimeData Hold TimeWrite Cycle TimeWE High Hold TimeAddress to Data Loading TimeSymboltCLS(1)tCLHtCS(1)tCHtWPtALS(1)tALHtDS(1)tDHtWCtWHtADL(2)Min155210100Max------------UnitnsnsnsnsnsnsnsnsnsnsnsnsNOTES : 1. The transition of the corresponding control pins must occur only once while WE is held low 2. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycleSamsung Confidential11K9F2G08U0C2.10

AC Characteristics for OperationParameterData Transfer from Cell to RegisterALE to RE DelayCLE to RE DelayReady to RE Low RE Pulse WidthWE High to BusyRead Cycle TimeRE Access TimeCE Access TimeRE High to Output Hi-ZCE High to Output Hi-ZCE High to ALE or CLE Don’t CareRE High to Output Hold

RE Low to Output Hold

CE High to Output Hold

RE High Hold TimeOutput Hi-Z to RE LowRE High to WE LowWE High to RE LowDevice Resetting Time(Read/Program/Erase)SymboltRtARtCLRtRRtRPtWBtRCtREAtCEAtRHZtCHZtCSDtRHOHtRLOHtCOHtREHtIRtRHWtWHRtRSTMin-10102015-30----60-

FLASH MEMORYMax35----100-202510030--------5/10/500(1)UnitµsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsµsNOTE : 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5µs.

Samsung Confidential12K9F2G08U0C3.0 NAND Flash Technical Notes3.1

Initial Invalid Block(s)

FLASH MEMORYInitial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung.

The information regarding the initial invalid block(s) is called the initial invalid block information. Devices with initial invalid block(s)

have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s)

does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select tran-sistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which is placed on

00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/528Byte ECC.

3.2

Identifying Initial Invalid Block(s)

All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The ini-tial invalid block(s) status is defined by the 1st byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every

initial invalid block has non-FFh data at the column address of 2048. Since the initial invalid block information is also erasable in most

cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the initial

invalid block(s) based on the original initial invalid block information and create the initial invalid block table via the following sug-gested flow chart(Figure 3). Any intentional erasure of the original initial invalid block information is prohibited. Start Set Block Address = 0Increment Block Address*Create (or update)Initial

Invalid Block(s) TableNoCheck "FFh"YesNoCheck "FFh" at the column address 2048

of the 1st and 2nd page in the blockLast Block ?YesEndFigure 3. Flow chart to create initial invalid block tableSamsung Confidential13K9F2G08U0CNAND Flash Technical Notes

(Continued)3.3

Error in write or read operation

FLASH MEMORYWithin its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual

following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail-ure after erase or program, block replacement should be done. Because program status fail during a page program does not affect

the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased

empty block and reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC must be

employed. To improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be

reclaimed by ECC without any block replacement. The said additional block failure rate does not include those reclaimed e Mode Write Read Erase Failure Program Failure

Single Bit FailureDetection and Countermeasure sequence Status Read after Erase --> Block Replacement

Status Read after Program --> Block Replacement Verify ECC -> ECC Correction

ECC: Error Correcting Code --> Hamming Code etc. Example) 1bit correction & 2bit detectionProgram Flow Chart StartWrite 80hWrite AddressWrite DataWrite 10hRead Status RegisterI/O 6 = 1 ?or R/B = 1 ?YesNoI/O 0 = 0 ?

No*Program Error

Yes Program Completed* : If program operation results in an error, map out

the block including the page in error and copy the target data to another g Confidential14K9F2G08U0CNAND Flash Technical Notes

(Continued)Erase Flow Chart StartWrite 60hWrite Block AddressWrite D0hRead Status Register

FLASH MEMORYRead Flow Chart StartWrite 00hWrite AddressWrite 30hRead DataECC GenerationI/O 6 = 1 ?or R/B = 1 ?YesNoNo*Erase Error

Reclaim the Error

Verify ECC

Yes Page Read CompletedNoI/O 0 = 0 ?

Yes Erase Completed : If erase operation results in an error, map out*

the failing block and replace it with another block.

Block Replacement1st(n-1)thnth(page)Block B2{{Block A1 an error occurs. Buffer memory of the controller.1st(n-1)thnth(page)* Step1When an error happens in the nth page of the Block ’A’ during erase or program operation.

* Step2Copy the data in the 1st ~ (n-1)th page to the same location of another free block. (Block ’B’)* Step3Then, copy the nth page data of the Block ’A’ in the buffer memory to the nth page of the Block ’B’.* Step4Do not erase or program to Block ’A’ by creating an ’invalid block’ table or other appropriate scheme.∼∼Samsung Confidential15K9F2G08U0C3.4 Addressing for program operation

FLASH MEMORYWithin a block, the pages must be programmed consecutively from the LSB(least significant bit) page of the block to the MSB(mostsignificant bit) pages of the block. Random page address programming is prohibited. In this case, the definition of LSB page is theLSB among the pages to be programmed. Therefore, LSB doesn't need to be page 63(64):Page 63(64):Page 31(32):Page 31(1):Page 2Page 1Page 0(3)(2)(1)Page 2Page 1Page 0(3)(32)(2)Data registerData registerFrom the LSB page to MSB pageDATA IN: Data (1)Data (64)Ex.) Random page program (Prohibition)DATA IN: Data (1)Data (64)Samsung Confidential16K9F2G08U0C4.0

System Interface Using CE don’t-care.

FLASH MEMORYFor an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal 2,112byte

data registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or

audio applications which use slow cycle time on the order of µ-seconds, de-activating CE during the data-loading and serial access

would provide significant savings in power 4. Program Operation with CE don’t-care.

≈≈CE don’t-care

≈≈≈≈I/Ox80hAddress(5Cycles)Data Input Data Input

≈ALE≈≈WE≈≈CE≈CLE10htCSCEtCCEtCEAtREAWEtWPREI/O0~7outFigure 5. Read Operation with CE don’t-care.

CE don’t-care

CEREALER/BtWEI/OXData Output(serial access)00hAddress(5Cycle)30hSamsung Confidential17≈≈≈≈≈≈CLEK9F2G08U0CNOTE

FLASH MEMORYI/OI/OxI/O 0 ~ I/O 7DATAData In/Out2,112byteCol. Add1A0~A7Col. Add2A8~A11ADDRESSRow Add1A12~A19Row Add2A20~A27Row Add3A28DeviceK9F2G08X0B4.1 Command Latch CycleCLEtCLtCtCLHtCHCEtWPWEtALSALEtDI/OxtALtDHCommand4.2

Address Latch CycletCLSCLEtCStWCCEtWCtWCtWCtWPWEtALSALEtDSI/OxtDHtWHtALHtWPtALStWHtALHtWPtALStWHtALHtWPtALStWHtALHtALStALHtDStDHtDStDHtDStDHtDStDHCol. Add1Col. Add2Row Add1Row Add2Row Add3Samsung Confidential18K9F2G08U0C4.3

Input Data Latch CycletCLH

FLASH MEMORY≈CLEtCHCEtWCALEtALSWEtDSI/OxtWHtDHtDStDH≈tWPtWP≈tWPtDHtDS≈DIN 0DIN 1DIN finaltRC* Serial Access Cycle after Read(CLE=L, WE=H, ALE=L)≈CEtREARE≈≈tREHtCHZtREAtCOH≈tREAtRHZI/OxtRRR/BNOTES : Transition is measured at ±200mV from steady state voltage with load. This parameter is sampled and not 100% tested. tRLOH is valid when frequency is higher than 33MHz.

tRHOH starts to be valid when frequency is lower than HOHDoutDoutDout≈≈Samsung Confidential19K9F2G08U0C4.4

Status Read CycletCLRCLEtCLStCSCEtCHtCEAtWHRREtDSI/OxtDHtIRtREAtCLH

FLASH MEMORYtWPWEtCHZtCOHtRHZtRHOH70h/F1hStatus OutputSamsung Confidential20K9F2G08U0C4.5

Read OperationtCLRCLE

FLASH MEMORYCEtWWEtWBtARALEtRREtRRI/Ox00h

Col. Add1Col. Add2Row Add1Row Add2Row Add3tCSDtRCtRHZ30h

≈≈≈Dout NDout N+1Dout MColumn AddressRow AddressBusyR/BSamsung Confidential21K9F2G08U0C4.6

Read Operation(Intercepted by CE)tCLRCLE

FLASH MEMORYCEtCSDWEtWBtARALEtRREtRRI/Ox00hCol. Add1Col. Add2Row Add1Row Add2Row Add330htCOHtCHZtRCDout NDout N+1Dout N+2Column AddressRow AddressR/BBusy4.7

Random Data Output In a Page

Samsung Confidential22CLEtCLRK9F2G08U0CCEWEtWBtARtRHWtWHRALEtRtRCtREAREtRRCol.

Add1Col.

Add2Row

Add1Row

Add2Row

Add3I/OxColumn

AddressBusyRow

Address00hDout

NDout

N+130h05hCol

Add1Col

Add2E0hDout

MDout

M+123Column

AddressR/BSamsung Confidential

FLASH MEMORYK9F2G08U0C4.8

Page Program Operation

FLASH MEMORYCLECEWEtADALEtWBtPROtWHRREDinDinNM1 up to m ByteSerial InputI/Ox80h≈≈≈tWCtWCtWCCo.l Add1Col. Add2Row Add1Row Add2Row Add310hProgramCommand70hRead StatusCommandI/O0SerialDataColumn AddressInput CommandRow Address≈R/BI/O0=0 Successful ProgramI/O0=1 Error in ProgramNOTES : tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data g Confidential244.9

Page

Program

Operation

with

Random

Data

InputK9F2G08U0C

CLECEtWCtADLtADL≈WEtWB≈tWCtWCtPROGtWHRALERESerial

DataColumn

AddressInput

CommandRow

Address≈≈Serial

InputRandom

DataColumn

AddressInput

CommandSerial

Input≈≈Samsung ConfidentialNOTES

tADL

the

time

from

the

rising

edge

final

address

cycle

the

rising

edge

first

data

cycle.≈25Col.

Add2Row

Add1Row

Add2Row

Add3I/OxCol.

Add1Col.

Add280h85hCol.

Add1DinNDinMDinJDinK10hProgramCommand70hRead

StatusCommandI/O0R/B

FLASH MEMORYK9F2G08U0C4.10

Copy-Back

Program

Operation

With

Random

Data

Input

CLECEtWCtWBtWBtRtADLtPROGtWHRWEALE≈≈≈BusyCopy-Back

DataInput

CommandBusyI/O0=0

Successful

ProgramI/O0=1

Error

ProgramSamsung Confidential

FLASH MEMORYNOTES

tADL

the

time

from

the

rising

edge

final

address

cycle

the

rising

edge

first

data

cycle.≈26Col

Add1Col

Add2Row

Add1Row

Add2Row

Add3REI/Ox35hColumn

Address00hColumn

AddressRow

Address85hCol

Add1Col

Add2Row

Add1Row

Add2Row

Add3Data

1Row

AddressData

N10h70hI/OxRead

Status

CommandR/BK9F2G08U0CCLECE≈≈tDBSYtWCWEtWBtWBtPROGtWHRALE4.11 Two- Plane Page Program operatoinRE≈≈≈≈I/Ox80hCol

Add1Col

Add2Row

Add1Row

Add2Row

Add3DinN81hCol

Add1Col

Add2Row

Add1Row

Add2Row

Add3DinMDinN70h/F1hI/OSerial

DataColumn

Address

Input

Command11hProgramPage

Row

Address1

2112

Byte

DataCommand(Dummy)Serial

InputDin10hM

Program

ConfirmCommand(True)Read

Status

Command

≈

typ.

500ns

max.

1µsEx.)

Two-Plane

Page

ProgramtDBSYtPROGR/B

80h

Address

Data

InputCol

Add1,2

Row

Add

1,2,32112

Byte

DataA0

A11

ValidA12

A17

Fixed

’Low’

A18

Fixed

’Low’

A19

A29

Fixed

’Low’11hNote≈R/B27

81hI/O0~7

Address

Data

InputCol

Add1,2

Row

Add

1,2,32112

Byte

DataA0

A11

ValidA12

A17

ValidA18

Fixed

’High’

A19

A29

Valid10h70h/F1hSamsung Confidential

FLASH MEMORYNote:

Any

command

between

11h

and

81h

prohibited

except

70h

and

FFh.K9F2G08U0C4.12

Block Erase Operation

FLASH MEMORYCLECEtWCWEtWBALEtBERStWHRREI/Ox60hRow Add1Row Add2Row Add3D0h70hI/O 0Row AddressAuto Block EraseSetup CommandErase Command≈R/BBusyRead StatusCommandI/O0=0 Successful EraseI/O0=1 Error in EraseSamsung Confidential28K9F2G08U0C4.13

Read ID Operation

FLASH MEMORYCLECEWEtARALEREtREAI/Ox90hRead ID Command00hAddress 1cycleEChDeviceCode3rd cyc.4th cyc.5th CodeDevice CodeDeviceK9F2G08U0CDevice Code (2nd Cycle)DAh3rd Cycle10h4th Cycle15h5th Cycle44hSamsung Confidential29K9F2G08U0CID Definition TableDescription1st

Byte2nd Byte3rd Byte4th

Byte5th

Byte

FLASH MEMORYMaker CodeDevice CodeInternal Chip Number, Cell Type, Number of Simultaneously Programmed Pages, EtcPage Size, Block Size,Redundant Area Size, Organization, Serial Access MinimumPlane Number, Plane Size3rd ID Data Description 1 2 4 8 2 Level Cell 4 Level Cell 8 Level Cell 16 Level Cell 1 2 4 8 Not Support Support Not Support Support 0 1 0 1

0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 I/O7 I/O6I/O5 I/O4I/O3 I/O2I/O1 I/O0 0 0 0 1 1 0 1 1 Internal Chip Number Cell Type Number of Simultaneously Programmed PagesInterleave ProgramBetween multiple chips Cache Program4th ID Data Description Page Size (w/o redundant area ) 1KB 2KB 4KB 8KB 64KB128KB256KB512KB 8 16 x8 x1650ns/30ns25nsReservedReserved 0 0 0 1 1 0 1 101 I/O7 I/O6I/O5 I/O4 I/O3I/O2I/O1 I/O00 00 11 01 1 Block Size (w/o redundant area ) Redundant Area Size ( byte/512byte)OrganizationSerial Access MinimumSamsung Confidential30K9F2G08U0C5th ID Data Description 1

64Mb128Mb256Mb512Mb1Gb2Gb4Gb8Gb 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 I/O7I/O6 I/O5 I/O4

FLASH MEMORYI/O3 I/O2 0 0 0 1 1 0 1 1 I/O1I/O0 Plane Number

Plane Size (w/o redundant Area)

Reserved 0 0Samsung Confidential31K9F2G08U0C5.0 Device Operation5.1

PAGE READ

FLASH MEMORYPage read is initiated by writing 00h-30h to the command register along with five address cycles. After initial power up, 00h commandis latched. Therefore only five address cycles and 30h command initiates that operation after initial power up. The 2,112 bytes of datawithin the selected page are transferred to the data registers in less than 35µs(tR). The system controller can detect the completion ofthis data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the data registers, they may be readout in 30ns cycle time by sequentially pulsing RE. The repetitive high to low transitions of the RE clock make the device output thedata starting from the selected column address up to the last column address.

The device may output random data in a page instead of the consecutive sequential data by writing random data output command.

The column address of next data, which is going to be out, may be changed to the address which follows random data output com-mand. Random data output can be operated multiple times regardless of how many times it is done in a 6. Read OperationALER/BREI/Ox00h≈≈≈WE≈CE≈CLEt≈Address(5Cycle)Col. Add.1,2 & Row Add.1,2,330hData Output(Serial Access)Data FieldSpare FieldSamsung Confidential32K9F2G08U0CFigure 7. Random Data Output In a Paget

FLASH MEMORYR/BREI/Ox00hAddress5Cycles30hData Output05hAddress2CyclesCol. Add.1,2E0hData OutputCol. Add.1,2 & Row Add.1,2,3Data FieldSpare FieldData FieldSpare Field5.2

PAGE PROGRAMThe device is programmed basically on a page basis, but it does allow multiple partial page programming of a word or consecutivebytes up to 2,112, in a single page program cycle. The number of consecutive partial page programming operation within the samepage without an intervening erase operation must not exceed 4 times for a single page. The addressing should be done in sequentialorder in a block. A page program cycle consists of a serial data loading period in which up to 2,112bytes of data may be loaded intothe data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell.

The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the five cycle address inputs and

then serial data loading. The words other than those to be programmed do not need to be loaded. The device supports random data

input in a page. The column address for the next data, which will be entered, may be changed to the address which follows random

data input command(85h). Random data input may be operated multiple times regardless of how many times it is done in a page. The

Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the serial

data will not initiate the programming process. The internal write state controller automatically executes the algorithms and timings

necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read

Status Register command may be entered to read the status register. The system controller can detect the completion of a program

cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset com-mand are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be

checked(Figure 8). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command

register remains in Read Status command mode until another valid command is written to the command 8. Program & Read Status OperationR/BI/Ox80hAddress & Data InputCol. Add.1,2 & Row Add.1,2,3DataFailtPROG"0"10h70hI/O0"1"PassSamsung Confidential33K9F2G08U0CFigure 9. Random Data Input In a PageR/BI/Ox80hAddress & Data InputCol. Add.1,2 & Row Add1,2,3DataAddress & Data InputCol. Add.1,2

Data

FLASH MEMORYtPROG"0"85h10h70hI/O0"1"FailPass5.3

Copy-Back ProgramCopy-Back program with Read for Copy-Back is configured to quickly and efficiently rewrite data stored in one page without data re-loading when the bit error is not in data stored. Since the time-consuming re-loading cycles are removed, the system performance isimproved. The benefit is especially obvious when a portion of a block is updated and the rest of the block also needs to be copied tothe newly assigned free block. Copy-Back operation is a sequential execution of Read for Copy-Back and of copy-back program withthe destination page address. A read operation with "35h" command and the address of the source page moves the whole 2,112-bytedata into the internal data buffer. A bit error is checked by sequential reading the data output. In the case where there is no bit error,the data do not need to be reloaded. Therefore Copy-Back program operation is initiated by issuing Page-Copy Data-Input command(85h) with destination page address. Actual programming operation begins after Program Confirm command (10h) is issued. Once theprogram process starts, the Read Status Register command (70h) may be entered to read the status register. The system controllercan detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. When theCopy-Back Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 10 & Figure 11). The command register remainsin Read Status command mode until another valid command is written to the command copy-back program, data modification is possible using random data input command (85h) as shown in 10. Page Copy-Back Program OperationR/BI/Ox00hAdd.(5Cycles)

35htRtPROG85hAdd.(5Cycles)

10h70hI/O0"1"Fail"0"PassCol. Add.1,2 & Row Add.1,2,3Source AddressCol. Add.1,2 & Row Add.1,2,3Destination AddressNote : Copy-Back Program operation is allowed only within the same memory plane.

Figure 11. Page Copy-Back Program Operation with Random Data InputR/BI/Ox00hAdd.(5Cycles)

35htRtPROG85hAdd.(5Cycles)

Data85hAdd.(2Cycles)

Col. Add.1,2

Data10h70hCol. Add.1,2 & Row Add.1,2,3Source AddressCol. Add.1,2 & Row Add.1,2,3Destination Address There is no limitation for the number of g Confidential34K9F2G08U0C5.4

READ STATUS

FLASH MEMORYThe device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether

the program or erase operation is completed successfully. After writing 70h/F1h command to the command register, a read cycle out-puts the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control

allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or

CE does not need to be toggled for updated status. Refer to Table 3 for specific Status Register definitions and Table 4 for specific F1h

Status Register definitions. The command register remains in Status Read mode until further commands are issued to it. Therefore, if

the status register is read during a random read cycle, the read command(00h) should be given before starting read 3. Read Status Register Definition for 70h CommandI/OI/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7Page ProgramPass/FailNot useNot useNot UseNot UseNot UseReady/BusyWrite ProtectBlock ErasePass/FailNot useNot useNot UseNot UseNot UseReady/BusyWrite ProtectReadNot useNot useNot useNot UseNot UseNot UseReady/BusyWrite ProtectDon’t -caredDon’t -caredDon’t -caredDon’t -caredDon’t -caredBusy : "0" Ready : "1"Protected : "0" Not Protected : "1"

DefinitionPass : "0" Fail : "1"NOTE : I/Os defined ’Not use’ are recommended to be masked out when Read Status is being 4. Read Status 2 Register Definition for F1h CommandI/O No.I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7Page ProgramChip Pass/FailPlane0 Pass/FailPlane1 Pass/FailNot UseNot UseNot UseReady/BusyWrite ProtectBlock EraseChip Pass/FailPlane0 Pass/FailPlane1 Pass/FailNot UseNot UseNot UseReady/BusyWrite ProtectReadNot useNot useNot useNot UseNot UseNot UseReady/BusyWrite ProtectDefinitionPass : "0" Fail : "1"Pass : "0" Fail : "1"Pass : "0" Fail : "1"Don’t -caredDon’t -caredDon’t -caredBusy : "0" Ready : "1"Protected : "0" Not Protected : "1"

NOTE : I/Os defined ’Not use’ are recommended to be masked out when Read Status is being g Confidential35K9F2G08U0C5.5

Read ID

FLASH MEMORYThe device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of

00h. Five read cycles sequentially output the manufacturer code(ECh), and the device code and 3rd, 4th, 5th cycle ID respectively.

The command register remains in Read ID mode until further commands are issued to it. Figure 18 shows the operation 17. Read ID Operation

CLECEWEtARALEtWHRREI/OX90htCLRtCEA00hAddress. 1cycletREAEChDeviceCodeDevice code3rd Cyc.4th Cyc.5th codeDeviceK9F2G08U0CDevice Code (2nd Cycle)DAh3rd Cycle10h4th Cycle15h5th Cycle44h5.6

RESETThe device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random

read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no

longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and

the Status Register is cleared to value C0h when WP is high. If the device is already in reset state a new reset command will be

accepted by the command register. The R/B pin changes to low for tRST after the Reset command is written. Refer to Figure 19

18. RESET OperationR/BI/OXFFhtRSAfter Power-upOperation mode 00h Command is latchedAfter ResetWaiting for next commandSamsung Confidential36K9F2G08U0C5.7

READY/BUSY

FLASH MEMORYThe device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read

completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command register or

random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an

open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and cur-rent drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig.19). Its value can be deter-mined by the following busy3.3V device - VOL : 0.4V, VOH : 2.4VReady VccR/Bopen drain outputVOHCL

VOLBusytftrGNDDeviceFigure 19. Rp vs tr ,tf & Rp vs ibusy@ Vcc = 3.3V, Ta = 25°C , CL = 50pF2.4200ntr,tf

[s]Ibusy1501.21000.82002mIbusy

[A]100ntr503.61m0.6tf3.63.63.61K2K3KRp(ohm)4KRp value guidanceVCC(Max.) - VOL(Max.)

IOL

+ ΣIL =3.2V8mA

+ ΣILRp(min, 3.3V part) =where IL

is the sum of the input currents of all devices tied to the R/B (max) is determined by maximum permissible limit of tr

Samsung Confidential37K9F2G08U0C6.0

Data Protection & Power up sequence

FLASH MEMORYThe device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector

disables all functions whenever Vcc is below about 2V(3.3V device). WP pin provides hardware protection and is recommended to

be kept at VIL

during power-up and power-down. A recovery time of minimum 100µs is required before internal circuit gets ready for

any command sequences as shown in Figure 20. The two step command sequence for program/erase provides additional software

19. AC Waveforms for Power Transition~ 2.3VVCCHigh≈~ 2.3VWPWE≈5 ms max100µsOpera-InvalidDon’t care≈Ready/Busy≈≈Don’t careNote :During the initialization, the device consumes a maximum current of 30mA (ICC1)Samsung Confidential38K9F2G08U0C7.0 Backward Compatibility Information

FLASH MEMORYThe below table shows key parameters which are different with previous product, so that the host could use make or modify its firm-ware without misunderstanding of compatibility. But the below table don’t have all the difference with previous product, but only keyparameters’ changing which can be defined to have an effect on developing NAND firmware or us Generation ProductPart IDK9F2G08U0B1. tR: 25us / tPROG(200us typ, 700us Max) tERS(1.5ms Typ, 10ms Max)2. tRC/tWC: 25ns3. 2 Plane Program: support4. 2Plane Copy-back Program: Support5. 2Plane Erase: Support6. EDO: Support1. ICC1 : 15mA(typ)/ 30mA(max)2. ICC2 : 15mA(typ)/ 30mA(max)3. ICC3 : 15mA(typ)/ 30mA(max)Current Generation DeviceK9F2G08U0C1. tR: 35us / tPROG(250us typ, 750us Max) tERS(2ms Typ, 10ms Max)2. tRC/tWC: 30ns3. 2 Plane Program: support4. 2Plane Copy-back Program: N/A5. 2Plane Erase: Support6. EDO: N/A1. ICC1 : 20mA(typ)/ 35mA(max)2. ICC2 : 20mA(typ)/ 35mA(max)3. ICC3 : 20mA(typ)/ 35mA(max)Features & OperationsAC & DC ParametersTechnical NotesSamsung Confidential39