2024年3月10日发(作者：伏友易)
Table 1‐4:Pin Definitions
TypeDirectionDescriptionPin Name
User I/O Pins
IO_L[1to24][PorN]_T[0to3] [UorL]_N[0to12]_ [multi-function]_[bank number] or
IO_T[0to3][UorL]_N[0to12]_[multi-function]_[bank number]
Most user I/O pins are capable of differential
signaling and can be implemented as pairs. Each
user I/O pin name consists of several indicator
labels, where:
•IO indicates a user I/O pin.
•L[1to24] indicates a unique differential pair with
P (positive) and N (negative) sides. User I/O pins
without the L indicator are single-ended.
Dedicated
Input/
Output
•T[0 to 3][U or L
] indicates the assigned byte group
and nibble location (upper or lower portion)
within that group for the pin.
•N[0 to 12] the number of the I/O within its byte
group.
•[multi-function] indicates any other functions that
the pin can provide. If not used for this function,
the pin can be a user I/O.
•[bank number] indicates the assigned bank for the
user I/O pin.
User I/O Multi-Function Pins
Four global clock (GC or HDGC) pin pairs are in each
bank. HDGC pins have direct access to the global
clock buffers. GC pins have direct access to the
global clock buffers and the MMCMs and PLLs that
are in the clock management tile (CMT) adjacent to
the same I/O bank. GC and HDGC inputs provide
dedicated, high-speed access to the internal global
and regional clock resources. GC and HDGC inputs
use dedicated routing and must be used for clock
inputs where the timing of various clocking features
is imperative.
Up-to-date information about designing with the GC
(or HDGC) pin is available in the UltraScale
Architecture Clocking Resources User Guide (UG572)
[Ref7]
This pin is for the DCI voltage reference resistor of P
transistor (per bank, to be pulled Low with a
reference resistor).
GC or HDGC
Multi-
function
Input
VRP
(1)
Multi-
function
N/A
Zynq UltraScale+ Packaging and Pinouts
UG1075 (v1.9) June 24, 2020
Chapter 1:Packaging Overview
Table 1‐4:Pin Definitions (Cont’d)
TypeDirectionDescription
Temperature-sensing diode pins (Anode: DXP;
Cathode: DXN). The thermal diode is accessed by
using the DXP and DXN pins. When not used, tie to
GND.
To use the thermal diode an appropriate external
thermal monitoring IC must be added. Consult the
external thermal monitoring IC data sheet for usage
guidelines.
Pin Name
Other Dedicated Pins
DXN
Dedicated
DXP
N/A
Zynq UltraScale+ Packaging and Pinouts
UG1075 (v1.9) June 24, 2020
Chapter 1:Packaging Overview
Footprint Compatibility between Packages
Zynq UltraScale+ devices are footprint compatible only with other Zynq UltraScale+ devices
with the same number of package pins and the same preceding alphabetic designator. For
example, XCZU9EG-FFVB1156 is compatible with the XCZU15EG-FFVB1156, but not with the
XCZU9EG-FFVC900. Pins that are available in one device but are not available in another
device are labeled as No Connects in the other device's package file.
IMPORTANT:
Footprint compatibility does not necessarily imply that all pins will function in the same
manner for different devices in a package. For limitations and guidelines on designing for footprint
compatible packages, refer to the Migration Between the Zynq UltraScale+ Devices and Packages
section of UltraScale Architecture PCB and Pin Planning User Guide (UG583) [Ref14].
Table1-5 shows the footprint compatible devices available for each package. See the
ZynqUltraScale+ MPSoC Overview (DS891) [Ref1] for specific package letter code options.
All packages are available with eutectic BGA balls. For these packages, the device type is XQ
and the Pb-free signifier in the package name is a Q.
Table 1‐5:
Packages
SBVA484
SFRA484
SFVA625
SFVC784
SFRC784
FBVB900
FFRB900
FFVC900
FFRC900
FFVB1156
FFRB1156
FFVC1156
FFRC1156
FFVD1156
FFVE1156
FSVE1156
FFVB1517XCZU11EG
XCZU7CG, XCZU7EG,
XCZU7EV, XQZU7EV
XCZU21DR, XQZU21DR
XCZU25DRXCZU27DR, XCZU43DR, XCZU28DR, XQZU28DR
XCZU47DR, XCZU49DR
XCZU17EGXCZU19EG, XQZU19EG
XCZU6CG, XCZU6EG
XCZU2CG, XCZU2EG,
XAZU2EG
XCZU2CG, XCZU2EG,
XAZU2EG
XCZU2CG, XCZU2EG,
XAZU2EG
XCZU4CG, XCZU4EG,
XCZU4EV
XCZU6CG, XCZU6EG
Footprint Compatibility
Footprint Compatible Devices
XCZU3CG, XCZU3EG,
XAZU3EG, XQZU3EG
XCZU3CG, XCZU3EG,
XAZU3EG
XCZU3CG, XCZU3EG,
XAZU3EG, XQZU3EG
XCZU5CG, XCZU5EG,
XCZU5EV, XQZU5EV
XCZU9CG, XCZU9EG,
XQZU9EG
XCZU9CG, XCZU9EG,
XQZU9EG
XCZU11EG, XQZU11EG
XCZU4CG, XCZU4EG,
XCZU4EV, XAZU4EV
XCZU7CG, XCZU7EG,
XCZU7EV, XAZU7EV,
XQZU7EV
XCZU15EG, XQZU15EG
XCZU15EG, XQZU15EG
XCZU5CG, XCZU5EG,
XCZU5EV, XAZU5EV,
XQZU5EV
Zynq UltraScale+ Packaging and Pinouts
UG1075 (v1.9) June 24, 2020
Chapter 1:Packaging Overview
Zynq UltraScale+ Packaging and Pinouts
UG1075 (v1.9) June 24, 2020
Chapter 1:Packaging Overview
Die Level Bank Numbering Overview
Banking and Clocking Summary
•For each device, not all banks are bonded out in every package.
GTH/GTY Columns
•
•
•
One GT Quad=Four transceivers=Four GTHE4 or GTYE4 primitives.
Not all GT Quads are bonded out in every package.
Also shown are quads labeled with RCAL. This specifies the location of the RCAL
masters for each device. With respect to the package, the RCAL masters are located on
the same package pin for each package, regardless of the device.
The XY coordinates shown in each quad correspond to the transceiver channel number
found in the pin names for that quad, as shown in Figure1-2.
An alphabetic designator is shown in each quad. Each letter corresponds to the
columns in Table1-6 and Table1-7.
The power supply group is shown in brackets [ ] for each quad.
•
•
•
I/O Banks
•Each user HP I/O bank has a total of 52 I/Os where 48 can be used as differential
(24differential pairs) or single-ended I/Os. The remaining four function only as
single-ended I/Os. All 52 pads of a bank are not always bonded out to pins.
A limited number of HP I/O banks have fewer than 52 SelectIO pins. These banks are
labeled as partial.
Each user HD I/O bank has a total of 24 I/Os that can be used as differential (12
differential pairs) or single-ended I/Os.
Adjacent to each bank is a physical layer (PHY) containing a CMT and other clock
resources.
Adjacent to each bank and PHY is a tile of logic resources that makes up a clock region.
Banks are arranged in columns and separated into rows which are pitch-matched with
adjacent PHY, clock regions, and GT blocks.
An alphabetic designator is shown in each bank. Each letter corresponds to the
columns in Table
1-6 and Table1-7.
•
•
•
•
•
•
Zynq UltraScale+ Packaging and Pinouts
UG1075 (v1.9) June 24, 2020
2024年3月10日发(作者：伏友易)
Table 1‐4:Pin Definitions
TypeDirectionDescriptionPin Name
User I/O Pins
IO_L[1to24][PorN]_T[0to3] [UorL]_N[0to12]_ [multi-function]_[bank number] or
IO_T[0to3][UorL]_N[0to12]_[multi-function]_[bank number]
Most user I/O pins are capable of differential
signaling and can be implemented as pairs. Each
user I/O pin name consists of several indicator
labels, where:
•IO indicates a user I/O pin.
•L[1to24] indicates a unique differential pair with
P (positive) and N (negative) sides. User I/O pins
without the L indicator are single-ended.
Dedicated
Input/
Output
•T[0 to 3][U or L
] indicates the assigned byte group
and nibble location (upper or lower portion)
within that group for the pin.
•N[0 to 12] the number of the I/O within its byte
group.
•[multi-function] indicates any other functions that
the pin can provide. If not used for this function,
the pin can be a user I/O.
•[bank number] indicates the assigned bank for the
user I/O pin.
User I/O Multi-Function Pins
Four global clock (GC or HDGC) pin pairs are in each
bank. HDGC pins have direct access to the global
clock buffers. GC pins have direct access to the
global clock buffers and the MMCMs and PLLs that
are in the clock management tile (CMT) adjacent to
the same I/O bank. GC and HDGC inputs provide
dedicated, high-speed access to the internal global
and regional clock resources. GC and HDGC inputs
use dedicated routing and must be used for clock
inputs where the timing of various clocking features
is imperative.
Up-to-date information about designing with the GC
(or HDGC) pin is available in the UltraScale
Architecture Clocking Resources User Guide (UG572)
[Ref7]
This pin is for the DCI voltage reference resistor of P
transistor (per bank, to be pulled Low with a
reference resistor).
GC or HDGC
Multi-
function
Input
VRP
(1)
Multi-
function
N/A
Zynq UltraScale+ Packaging and Pinouts
UG1075 (v1.9) June 24, 2020
Chapter 1:Packaging Overview
Table 1‐4:Pin Definitions (Cont’d)
TypeDirectionDescription
Temperature-sensing diode pins (Anode: DXP;
Cathode: DXN). The thermal diode is accessed by
using the DXP and DXN pins. When not used, tie to
GND.
To use the thermal diode an appropriate external
thermal monitoring IC must be added. Consult the
external thermal monitoring IC data sheet for usage
guidelines.
Pin Name
Other Dedicated Pins
DXN
Dedicated
DXP
N/A
Zynq UltraScale+ Packaging and Pinouts
UG1075 (v1.9) June 24, 2020
Chapter 1:Packaging Overview
Footprint Compatibility between Packages
Zynq UltraScale+ devices are footprint compatible only with other Zynq UltraScale+ devices
with the same number of package pins and the same preceding alphabetic designator. For
example, XCZU9EG-FFVB1156 is compatible with the XCZU15EG-FFVB1156, but not with the
XCZU9EG-FFVC900. Pins that are available in one device but are not available in another
device are labeled as No Connects in the other device's package file.
IMPORTANT:
Footprint compatibility does not necessarily imply that all pins will function in the same
manner for different devices in a package. For limitations and guidelines on designing for footprint
compatible packages, refer to the Migration Between the Zynq UltraScale+ Devices and Packages
section of UltraScale Architecture PCB and Pin Planning User Guide (UG583) [Ref14].
Table1-5 shows the footprint compatible devices available for each package. See the
ZynqUltraScale+ MPSoC Overview (DS891) [Ref1] for specific package letter code options.
All packages are available with eutectic BGA balls. For these packages, the device type is XQ
and the Pb-free signifier in the package name is a Q.
Table 1‐5:
Packages
SBVA484
SFRA484
SFVA625
SFVC784
SFRC784
FBVB900
FFRB900
FFVC900
FFRC900
FFVB1156
FFRB1156
FFVC1156
FFRC1156
FFVD1156
FFVE1156
FSVE1156
FFVB1517XCZU11EG
XCZU7CG, XCZU7EG,
XCZU7EV, XQZU7EV
XCZU21DR, XQZU21DR
XCZU25DRXCZU27DR, XCZU43DR, XCZU28DR, XQZU28DR
XCZU47DR, XCZU49DR
XCZU17EGXCZU19EG, XQZU19EG
XCZU6CG, XCZU6EG
XCZU2CG, XCZU2EG,
XAZU2EG
XCZU2CG, XCZU2EG,
XAZU2EG
XCZU2CG, XCZU2EG,
XAZU2EG
XCZU4CG, XCZU4EG,
XCZU4EV
XCZU6CG, XCZU6EG
Footprint Compatibility
Footprint Compatible Devices
XCZU3CG, XCZU3EG,
XAZU3EG, XQZU3EG
XCZU3CG, XCZU3EG,
XAZU3EG
XCZU3CG, XCZU3EG,
XAZU3EG, XQZU3EG
XCZU5CG, XCZU5EG,
XCZU5EV, XQZU5EV
XCZU9CG, XCZU9EG,
XQZU9EG
XCZU9CG, XCZU9EG,
XQZU9EG
XCZU11EG, XQZU11EG
XCZU4CG, XCZU4EG,
XCZU4EV, XAZU4EV
XCZU7CG, XCZU7EG,
XCZU7EV, XAZU7EV,
XQZU7EV
XCZU15EG, XQZU15EG
XCZU15EG, XQZU15EG
XCZU5CG, XCZU5EG,
XCZU5EV, XAZU5EV,
XQZU5EV
Zynq UltraScale+ Packaging and Pinouts
UG1075 (v1.9) June 24, 2020
Chapter 1:Packaging Overview
Zynq UltraScale+ Packaging and Pinouts
UG1075 (v1.9) June 24, 2020
Chapter 1:Packaging Overview
Die Level Bank Numbering Overview
Banking and Clocking Summary
•For each device, not all banks are bonded out in every package.
GTH/GTY Columns
•
•
•
One GT Quad=Four transceivers=Four GTHE4 or GTYE4 primitives.
Not all GT Quads are bonded out in every package.
Also shown are quads labeled with RCAL. This specifies the location of the RCAL
masters for each device. With respect to the package, the RCAL masters are located on
the same package pin for each package, regardless of the device.
The XY coordinates shown in each quad correspond to the transceiver channel number
found in the pin names for that quad, as shown in Figure1-2.
An alphabetic designator is shown in each quad. Each letter corresponds to the
columns in Table1-6 and Table1-7.
The power supply group is shown in brackets [ ] for each quad.
•
•
•
I/O Banks
•Each user HP I/O bank has a total of 52 I/Os where 48 can be used as differential
(24differential pairs) or single-ended I/Os. The remaining four function only as
single-ended I/Os. All 52 pads of a bank are not always bonded out to pins.
A limited number of HP I/O banks have fewer than 52 SelectIO pins. These banks are
labeled as partial.
Each user HD I/O bank has a total of 24 I/Os that can be used as differential (12
differential pairs) or single-ended I/Os.
Adjacent to each bank is a physical layer (PHY) containing a CMT and other clock
resources.
Adjacent to each bank and PHY is a tile of logic resources that makes up a clock region.
Banks are arranged in columns and separated into rows which are pitch-matched with
adjacent PHY, clock regions, and GT blocks.
An alphabetic designator is shown in each bank. Each letter corresponds to the
columns in Table
1-6 and Table1-7.
•
•
•
•
•
•
Zynq UltraScale+ Packaging and Pinouts
UG1075 (v1.9) June 24, 2020