2024年3月17日发(作者：伏友易)

Chapter 11:Designing with the Core

In Figure11-8, the read data returned is always in the same order as the requests made on

the address/control bus.

Periodic Reads

The FPGA DDR PHY requires two back-to-back DRAM RD or RDA command to be issued

every 1µs. This requirement is described in the User Interface. When the controller is

writing and the 1 µs periodic reads are due, the reads are injected by the controller to the

address of the next read/write in the queue. When the controller is idle and no reads or

writes are requested, the periodic reads use the last address accessed. If this address has

been closed, an activate is required. This injected read is issued to the DRAM following the

normal mechanisms of the controller issuing transactions. The key difference is that no read

data is returned to the UI. This is wasted DRAM bandwidth.

User interface patterns with long strings of write transactions are affected the most by the

PHY periodic read requirement. Consider a pattern with a 50/50 read/write transaction

ratio, but organized such that the pattern alternates between 2 µs bursts of 100% page hit

reads and 2 µs bursts of 100% page hit writes. The periodic reads are injected in the 2 µs

write burst, resulting in a loss of efficiency due to the read command and the turnaround

time to switch the DRAM and DDR bus from writes to reads back to writes. This 2 µs

alternating burst pattern is slightly more efficient than alternating between reads and

writes every 1 µs. A 1 µs or shorter alternating pattern would eliminate the need for the

controller to inject reads, but there would still be more read-write turnarounds.

Bus turnarounds are expensive in terms of efficiency and should be avoided if possible.

Long bursts of page hit writes, > 2 µs in duration, are still the most efficient way to write to

the DRAM, but the impact of one write-read-write turnaround each 1 µs must be taken into

account when calculating the maximum write efficiency.

UltraScale Architecture-Based FPGAs Memory IP v1.4

PG150 January 21, 2021

2024年3月17日发(作者：伏友易)

Chapter 11:Designing with the Core

In Figure11-8, the read data returned is always in the same order as the requests made on

the address/control bus.

Periodic Reads

The FPGA DDR PHY requires two back-to-back DRAM RD or RDA command to be issued

every 1µs. This requirement is described in the User Interface. When the controller is

writing and the 1 µs periodic reads are due, the reads are injected by the controller to the

address of the next read/write in the queue. When the controller is idle and no reads or

writes are requested, the periodic reads use the last address accessed. If this address has

been closed, an activate is required. This injected read is issued to the DRAM following the

normal mechanisms of the controller issuing transactions. The key difference is that no read

data is returned to the UI. This is wasted DRAM bandwidth.

User interface patterns with long strings of write transactions are affected the most by the

PHY periodic read requirement. Consider a pattern with a 50/50 read/write transaction

ratio, but organized such that the pattern alternates between 2 µs bursts of 100% page hit

reads and 2 µs bursts of 100% page hit writes. The periodic reads are injected in the 2 µs

write burst, resulting in a loss of efficiency due to the read command and the turnaround

time to switch the DRAM and DDR bus from writes to reads back to writes. This 2 µs

alternating burst pattern is slightly more efficient than alternating between reads and

writes every 1 µs. A 1 µs or shorter alternating pattern would eliminate the need for the

controller to inject reads, but there would still be more read-write turnarounds.

Bus turnarounds are expensive in terms of efficiency and should be avoided if possible.

Long bursts of page hit writes, > 2 µs in duration, are still the most efficient way to write to

the DRAM, but the impact of one write-read-write turnaround each 1 µs must be taken into

account when calculating the maximum write efficiency.

UltraScale Architecture-Based FPGAs Memory IP v1.4

PG150 January 21, 2021