2024年3月22日发(作者：司沛白)
Using Xilinx CPLDs to Interface to a NAND Flash Memory Device
in order to decode the flash interface commands. The interface signals to the Flash device are
asserted by writing to a specific port of the CPLD.
CE#
ADDR[3:0]
WRITE#
READ#
CE#
RESET
RY/BY#
CoolRunner
XPLA3 CPLD
RE#
WE#
SE#
ALE
CLE
WP#
AMD UltraNAND
(AM30LV0064D)
or
Samsung
(K9F4008W0A)
I/O[7:0]
RY/BY#
X354_02_082701
Figure 1: System Block Diagram
The NAND Flash interface signals and functionality is shown in Table1.
Table 1: UltraNAND Pin Descriptions
Pin Name
I/O[7:0]
CLE
Function
I/O pins used to send commands, address, and data to the
device, and receive data during read operations.
Command Latch Enable. The CLE input controls writing to the
command register. When CLE is high, the command is loaded on
the rising edge of WE#.
Address Latch Enable. The ALE input controls writing to the
address register. When ALE is high, the address is loaded on the
rising edge of WE#. ALE must remain high during the entire
address sequence.
Chip Enable. The CE# input controls the active vs. standby
mode of the device. During a command or address load
sequence, CE# must be low prior to the falling edge of WE#.
Read Enable. The RE# input controls the data and status output
on the I/O lines. The data output is triggered on the falling edge
of RE#.
Write Enable. The WE# input controls the data and command on
the I/O lines during a write sequence. The I/O lines are latched
on the rising edge of the WE# signal.
Write Protect. The WP# input provides protection when
programming or erasing the device. The internal voltage
regulator is reset when WP# is low, preventing any program or
erase operations.
Spare Area Enable. The SE# input controls access to the 16
bytes of spare area on each page. When SE# is not asserted
(high), the spare area for the selected page is not enabled. When
SE# is asserted (low), access to the spare area is enabled.
Ready/Busy Output. The RY/BY# output indicates the operation
status of the device. When RY/BY# is high, the device is ready
for the next operation. When RY/BY# is low, an internal program,
erase, or random read operation is in progress.
ALE
CE#
RE#
WE#
WP#
SE#
RY/BY#
XAPP354 (v1.1) September 30, 2002
XC2C128 CoolRunner-II CPLD
Pin Descriptions (Continued)
Function
Block
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
Macro-
cell
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VQ100CP132TQ144
77
78
-
79
80
81
-
-
-
-
82
-
85
86
87
89
C12
B12
A12
C11
B11
A11
C10
-
-
-
A10
C9
A8
B8
C8
B7
112
113
115
116
117
118
119
-
-
-
120
121
124
125
126
128
I/O
Bank
2
2
2
2
2
2
2
-
-
-
2
2
2
2
2
2
Pin Descriptions (Continued)
Function
Block
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
Macro-
cell
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VQ100CP132TQ144
-
53
52
50
-
49
-
-
-
-
-
46
44
43
42
41
N14
N13
P14
P12
M11
N11
-
-
-
-
P11
P10
P9
M8
N8
P8
77
76
74
71
70
69
-
-
-
-
68
64
61
60
59
58
I/O
Bank
1
1
1
1
1
1
-
-
-
-
1
1
1
1
1
1
Notes:
= global output enable, GSR = global reset/set, GCK =
global clock, CDRST = clock divide reset, DGE = DataGATE
enable.
XC2C128 JTAG, Power/Ground, No Connect Pins and Total User I/O
Pin Type
TCK
TDI
TDO
TMS
V
CCAUX
(JTAG supply voltage)
Power internal (V
CC
)
Power Bank 1 I/O (V
CCIO1
)
Power Bank 2 I/O (V
CCIO2
)
Ground
No connects
VQ100
(1)
48
45
83
47
5
26, 57
20, 38, 51
88, 98
21, 25, 31, 62, 69, 75,
84, 100
-
CP132
(1)
M10
M9
B9
N10
D3
P1, K12, A2
J3, P7, G14, P13
A14, C4, A7
K2, N1, P4, N9, N12, J14,
H14, E14, B14, A9, B3
L1, L3, M1, N4, C13, B10
TQ144
(1)
67
63
122
65
8
1, 37, 84
27, 55, 73, 93
109, 127, 141
29, 36, 47, 62, 72, 89, 90,
99, 108, 123, 144
18, 20, 31, 33, 34, 42, 44,
46, 48, 66, 75, 106, 107,
114, 135, 137, 139, 142
100Total user I/O (including dual function
pins)
80100
Notes:
compatible with all larger and smaller densities except where I/O banking is used.
DS093 (v2.9) June 28, 2005
Product Specification
2024年3月22日发(作者：司沛白)
Using Xilinx CPLDs to Interface to a NAND Flash Memory Device
in order to decode the flash interface commands. The interface signals to the Flash device are
asserted by writing to a specific port of the CPLD.
CE#
ADDR[3:0]
WRITE#
READ#
CE#
RESET
RY/BY#
CoolRunner
XPLA3 CPLD
RE#
WE#
SE#
ALE
CLE
WP#
AMD UltraNAND
(AM30LV0064D)
or
Samsung
(K9F4008W0A)
I/O[7:0]
RY/BY#
X354_02_082701
Figure 1: System Block Diagram
The NAND Flash interface signals and functionality is shown in Table1.
Table 1: UltraNAND Pin Descriptions
Pin Name
I/O[7:0]
CLE
Function
I/O pins used to send commands, address, and data to the
device, and receive data during read operations.
Command Latch Enable. The CLE input controls writing to the
command register. When CLE is high, the command is loaded on
the rising edge of WE#.
Address Latch Enable. The ALE input controls writing to the
address register. When ALE is high, the address is loaded on the
rising edge of WE#. ALE must remain high during the entire
address sequence.
Chip Enable. The CE# input controls the active vs. standby
mode of the device. During a command or address load
sequence, CE# must be low prior to the falling edge of WE#.
Read Enable. The RE# input controls the data and status output
on the I/O lines. The data output is triggered on the falling edge
of RE#.
Write Enable. The WE# input controls the data and command on
the I/O lines during a write sequence. The I/O lines are latched
on the rising edge of the WE# signal.
Write Protect. The WP# input provides protection when
programming or erasing the device. The internal voltage
regulator is reset when WP# is low, preventing any program or
erase operations.
Spare Area Enable. The SE# input controls access to the 16
bytes of spare area on each page. When SE# is not asserted
(high), the spare area for the selected page is not enabled. When
SE# is asserted (low), access to the spare area is enabled.
Ready/Busy Output. The RY/BY# output indicates the operation
status of the device. When RY/BY# is high, the device is ready
for the next operation. When RY/BY# is low, an internal program,
erase, or random read operation is in progress.
ALE
CE#
RE#
WE#
WP#
SE#
RY/BY#
XAPP354 (v1.1) September 30, 2002
XC2C128 CoolRunner-II CPLD
Pin Descriptions (Continued)
Function
Block
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
Macro-
cell
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VQ100CP132TQ144
77
78
-
79
80
81
-
-
-
-
82
-
85
86
87
89
C12
B12
A12
C11
B11
A11
C10
-
-
-
A10
C9
A8
B8
C8
B7
112
113
115
116
117
118
119
-
-
-
120
121
124
125
126
128
I/O
Bank
2
2
2
2
2
2
2
-
-
-
2
2
2
2
2
2
Pin Descriptions (Continued)
Function
Block
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
Macro-
cell
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VQ100CP132TQ144
-
53
52
50
-
49
-
-
-
-
-
46
44
43
42
41
N14
N13
P14
P12
M11
N11
-
-
-
-
P11
P10
P9
M8
N8
P8
77
76
74
71
70
69
-
-
-
-
68
64
61
60
59
58
I/O
Bank
1
1
1
1
1
1
-
-
-
-
1
1
1
1
1
1
Notes:
= global output enable, GSR = global reset/set, GCK =
global clock, CDRST = clock divide reset, DGE = DataGATE
enable.
XC2C128 JTAG, Power/Ground, No Connect Pins and Total User I/O
Pin Type
TCK
TDI
TDO
TMS
V
CCAUX
(JTAG supply voltage)
Power internal (V
CC
)
Power Bank 1 I/O (V
CCIO1
)
Power Bank 2 I/O (V
CCIO2
)
Ground
No connects
VQ100
(1)
48
45
83
47
5
26, 57
20, 38, 51
88, 98
21, 25, 31, 62, 69, 75,
84, 100
-
CP132
(1)
M10
M9
B9
N10
D3
P1, K12, A2
J3, P7, G14, P13
A14, C4, A7
K2, N1, P4, N9, N12, J14,
H14, E14, B14, A9, B3
L1, L3, M1, N4, C13, B10
TQ144
(1)
67
63
122
65
8
1, 37, 84
27, 55, 73, 93
109, 127, 141
29, 36, 47, 62, 72, 89, 90,
99, 108, 123, 144
18, 20, 31, 33, 34, 42, 44,
46, 48, 66, 75, 106, 107,
114, 135, 137, 139, 142
100Total user I/O (including dual function
pins)
80100
Notes:
compatible with all larger and smaller densities except where I/O banking is used.
DS093 (v2.9) June 28, 2005
Product Specification