2024年4月26日发(作者：訾花)
Virtex-II Platform FPGAs:
Functional Description
DS031-2 (v4.0) April 7, 2014Product Specification
Detailed Description
Input/Output Blocks (IOBs)
Virtex-II™ I/O blocks (IOBs) are provided in groups of two or
four on the perimeter of each device. Each IOB can be used
as input and/or output for single-ended I/Os. Two IOBs can
be used as a differential pair. A differential pair is always
connected to the same switch matrix, as shown in Figure1.
IOB blocks are designed for high performances I/Os, sup-
porting 19 single-ended standards, as well as differential
signaling with LVDS, LDT, Bus LVDS, and LVPECL.
Table 1: Supported Single-Ended I/O Standards
IOSTANDARD
Attribute
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
PCI33_3
Output
V
CCO
3.3
3.3
2.5
1.8
1.5
3.3
3.3
3.3
Note (1)
Note (1)
1.5
Input
V
CCO
3.3
3.3
2.5
1.8
1.5
3.3
3.3
3.3
Note (1)
Note (1)
N/R
Input
V
REF
N/R
(3)
N/R
N/R
N/R
N/R
N/R
N/R
N/R
0.8
1.0
0.75
0.75
0.9
0.9
0.9
0.9
1.1
1.1
0.9
0.9
1.25
1.25
1.5
1.5
Board
Termination
Voltage (V
TT
)
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
1.2
1.5
0.75
0.75
1.5
1.5
0.9
0.9
1.8
1.8
0.9
0.9
1.25
1.25
1.5
1.5
IOB
PAD4
Differential Pair
Switch
Matrix
IOB
PAD3
IOB
PAD2
Differential Pair
IOB
PAD1
DS031_30_101600
PCI66_3
PCI-X
GTL
GTLP
HSTL_I
HSTL_II
HSTL_III
HSTL_IV
HSTL_I_18
HSTL_II_18
HSTL_III _18
HSTL_IV_18
SSTL18_I
(2)
SSTL18_II
SSTL2_I
SSTL2_II
SSTL3_I
SSTL3_II
1.5 N/R
1.5 N/R
1.5 N/R
1.8 N/R
1.8 N/R
1.8
1.8
1.8
2.5
2.5
3.3
3.3
N/R
N/R
N/R
N/R
N/R
N/R
N/R
1.8 N/R
Figure 1: Virtex-II Input/Output Tile
Note: Differential I/Os must use the same clock.
Supported I/O Standards
Virtex-II IOB blocks feature SelectI/O-Ultra inputs and out-
puts that support a wide variety of I/O signaling standards.
In addition to the internal supply voltage (V
CCINT
=1.5V),
output driver supply voltage (V
CCO
) is dependent on the I/O
standard (see Table 1 and Table 2). An auxiliary supply volt-
age (V
CCAUX
= 3.3 V) is required, regardless of the I/O
standard used. For exact supply voltage absolute maximum
ratings, see DC Input and Output Levels in Module 3.
All of the user IOBs have fixed-clamp diodes to V
CCO
and to
AGP-2X/AGP3.3N/R1.32N/R
ground. As outputs, these IOBs are not compatible or com-
Notes:
pliant with 5V I/O standards. As inputs, these IOBs are not
1.V
CCO
of GTL or GTLP should not be lower than the termination
normally 5V tolerant, but can be used with 5V I/O standards
voltage or the voltage seen at the I/O pad. Example: If the pin High
level is 1.5V, connect V
CCO
to 1.5V.
when external current-limiting resistors are used. For more
18_I is not a JEDEC-supported standard.
details, see the “5V Tolerant I/Os“ Tech Topic.
3.N/R = no requirement.
Table 3 lists supported I/O standards with Digitally Con-
trolled Impedance. See Digitally Controlled Impedance
(DCI), page 8.
DS031-2 (v4.0) April 7, 2014
Product Specification
Virtex-II Platform FPGAs: Functional Description
Table 13: Virtex-II Logic Resources Available in All CLBs
CLB Array:
Row x
Column
8 x 8
16 x 8
24 x 16
32 x 24
40 x 32
48 x 40
56 x 48
64 x 56
80 x 72
96 x 88
112 x 104
Number Number
of of
SlicesLUTs
256
512
1,536
3,072
5,120
7,680
10,752
14,336
23,040
33,792
46,592
512
1,024
3,072
6,144
10,240
15,360
21,504
28,672
46,080
67,584
93,184
Max Distributed
SelectRAM or Shift
Register (bits)
8,192
16,384
49,152
98,304
163,840
245,760
344,064
458,752
737,280
1,081,344
1,490,944
Number
of
Flip-Flops
512
1,024
3,072
6,144
10,240
15,360
21,504
28,672
46,080
67,584
93,184
Number
of
Carry-Chains
(1)
16
16
32
48
64
80
96
112
144
176
208
Number
of SOP
Chains
(1)
16
32
48
64
80
96
112
128
160
192
224
Device
XC2V40
XC2V80
XC2V250
XC2V500
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
DS031-2 (v4.0) April 7, 2014
Product Specification
Virtex-II Platform FPGAs: Functional Description
Virtex-II FPGA device. Timing is similar to the Slave Serial-
MAP mode except that CCLK is supplied by the Virtex-II
FPGA.
IEEE 1532 standard for In-System Configurable (ISC)
devices. The IEEE 1532 standard is backward compliant
with the IEEE 1149.1-1993 TAP and state machine. The
IEEE Standard 1532 for In-System Configurable (ISC)
devices is intended to be programmed, reprogrammed, or
tested on the board via a physical and logical protocol.
Configuration through the Boundary-Scan port is always
available, independent of the mode selection. Selecting the
Boundary-Scan mode simply turns off the other modes.
Boundary-Scan (JTAG, IEEE 1532) Mode
In Boundary-Scan mode, dedicated pins are used for con-
figuring the Virtex-II device. The configuration is done
entirely through the IEEE 1149.1 Test Access Port (TAP).
Virtex-II device configuration using Boundary-Scan is com-
patible with the IEEE 1149.1-1993 standard and the new
Table
25: Virtex-II Configuration Mode Pin Settings
Configuration Mode
(1)
Master Serial
Slave Serial
Master SelectMAP
Slave SelectMAP
oundary-Scan
M2
0
1
0
1
1
M1
0
1
1
1
0
M0
0
1
1
0
1
CCLK Direction
Out
In
Out
In
N/A
Data Width
1
1
8
8
1
Serial D
OUT
(2)
Yes
Yes
No
No
No
DS031-2 (v4.0) April 7, 2014
Product Specification
Virtex-II Platform FPGAs: DC and Switching Characteristics
Table 5: Minimum Power On Current Required for Virtex-II Devices
Device (mA)
XC2V40, XC2V80,
XC2V250, XC2V500
I
CCINTMIN
I
CCAUXMIN
I
CCOMIN
200
100
50
XC2V1000
250
100
50
XC2V1500
350
100
100
XC2V2000
400
100
100
XC2V3000
500
100
100
XC2V4000
650
100
100
XC2V6000
800
100
100
XC2V8000
1100
100
100
Notes:
specified for power on current parameters are Commercial Grade. For Industrial Grade values, multiply Commercial Grade
values by 1.25.
2.I
CCOMIN
values listed here apply to the entire device (all banks).
General Power Supply Requirements
Proper decoupling of all FPGA power supplies is sessential.
Consult Xilinx Application Note
XAPP623
for detailed infor-
mation on power distribution system design.
V
CCAUX
powers critical resources in the FPGA. Thus,
V
CCAUX
is especially susceptible to power supply noise.
Changes in V
CCAUX
voltage outside of 200 mV peak to peak
should take place at a rate no faster than 10 mV per milli-
second. Techniques to help reduce jitter and period distor-
tion are provided in Xilinx Answer Record 13756.
V
CCAUX
can share a power plane with 3.3V V
CCO
, but only if
V
CCO
does not have excessive noise. Using simultaneously
switching output (SSO) limits are essential for keeping
power supply noise to a minimum. Refer to
XAPP689
, “Man-
aging Ground Bounce in Large FPGAs,” to determine the
number of simultaneously switching outputs allowed per
bank at the package level.
DC Input and Output Levels
Values for V
IL
and V
IH
are recommended input voltages.
Values for I
OL
and I
OH
are guaranteed over the recom-
mended operating conditions at the V
OL
and V
OH
test
points. Only selected standards are tested. These are cho-
Table 6: DC Input and Output Levels
Input/Output
Standard
LVTTL
(1)
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
PCI33_3
PCI66_3
PCI–X
GTLP
GTL
HSTL I
HSTL II
HSTL III
HSTL IV
sen to ensure that all standards meet their specifications.
The selected standards are tested at minimum V
CCO
with
the respective V
OL
and V
OH
voltage levels shown. Other
standards are sample tested.
V
IL
V, Min
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
V
IH
V, Min
2.0
2.0
1.7
65% V
CCO
65% V
CCO
50% V
CCO
50% V
CCO
Note 2
V
REF
+ 0.1
V
REF
+ 0.05
V
REF
+ 0.1
V
REF
+ 0.1
V
REF
+ 0.1
V
REF
+ 0.1
V
OL
V, Max
3.6
3.6
2.7
1.95
1.7
V
CCO
+ 0.5
V
CCO
+ 0.5
Note 2
V
CCO
+ 0.5
V
CCO
+ 0.5
V
CCO
+ 0.5
V
CCO
+ 0.5
V
CCO
+ 0.5
V
CCO
+ 0.5
V
OH
V, Min
2.4
V
CCO
–0.4
V
CCO
–0.4
V
CCO
–0.4
V
CCO
–0.4
90% V
CCO
90% V
CCO
Note 2
n/a
n/a
V
CCO
–0.4
V
CCO
–0.4
V
CCO
–0.4
V
CCO
–0.4
I
OL
mA
24
24
24
16
16
Note 2
Note 2
Note 2
36
40
8
16
24
48
I
OH
mA
–24
–24
–24
–16
–16
Note 2
Note 2
Note 2
n/a
n/a
–8
–16
–8
–8
V, Max
0.8
0.8
0.7
35% V
CCO
35% V
CCO
30% V
CCO
30% V
CCO
Note 2
V
REF
–0.1
V
REF
–0.05
V
REF
–0.1
V
REF
–0.1
V
REF
–0.1
V
REF
–0.1
V, Max
0.4
0.4
0.4
0.4
0.4
10% V
CCO
10% V
CCO
Note 2
0.6
0.4
0.4
0.4
0.4
0.4
DS031-3 (v4.0) April 7, 2014
Product Specification
Virtex-II Platform FPGAs: DC and Switching Characteristics
Table 6: DC Input and Output Levels (Continued)
Input/Output
Standard
SSTL3 I
SSTL3 II
SSTL2 I
SSTL2 II
AGP
V
IL
V, Min
–0.5
–0.5
–0.5
–0.5
–0.5
V
IH
V, Min
V
REF
+ 0.2
V
REF
+ 0.2
V
REF
+ 0.15
V
REF
+ 0.15
V
REF
+ 0.2
V
OL
V, Max
V
CCO
+ 0.5
V
CCO
+ 0.5
V
CCO
+ 0.5
V
CCO
+ 0.5
V
CCO
+ 0.5
V
OH
V, Min
V
REF
+ 0.6
V
REF
+ 0.8
V
REF
+ 0.65
V
REF
+ 0.80
90% V
CCO
I
OL
mA
8
16
7.6
15.2
Note 2
I
OH
mA
–8
–16
–7.6
–15.2
Note 2
V, Max
V
REF
–0.2
V
REF
–0.2
V
REF
–0.15
V
REF
–0.15
V
REF
–0.2
V, Max
V
REF
–0.6
V
REF
–0.8
V
REF
–0.65
V
REF
–0.80
10% V
CCO
Notes:
1.V
OL
and V
OH
for lower drive currents are sample tested. The DONE pin is always LVTTL 12 mA.
according to the relevant specifications.
and LVCMOS inputs have approximately 100 mV of hysteresis.
DS031-3 (v4.0) April 7, 2014
Product Specification
2024年4月26日发(作者：訾花)
Virtex-II Platform FPGAs:
Functional Description
DS031-2 (v4.0) April 7, 2014Product Specification
Detailed Description
Input/Output Blocks (IOBs)
Virtex-II™ I/O blocks (IOBs) are provided in groups of two or
four on the perimeter of each device. Each IOB can be used
as input and/or output for single-ended I/Os. Two IOBs can
be used as a differential pair. A differential pair is always
connected to the same switch matrix, as shown in Figure1.
IOB blocks are designed for high performances I/Os, sup-
porting 19 single-ended standards, as well as differential
signaling with LVDS, LDT, Bus LVDS, and LVPECL.
Table 1: Supported Single-Ended I/O Standards
IOSTANDARD
Attribute
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
PCI33_3
Output
V
CCO
3.3
3.3
2.5
1.8
1.5
3.3
3.3
3.3
Note (1)
Note (1)
1.5
Input
V
CCO
3.3
3.3
2.5
1.8
1.5
3.3
3.3
3.3
Note (1)
Note (1)
N/R
Input
V
REF
N/R
(3)
N/R
N/R
N/R
N/R
N/R
N/R
N/R
0.8
1.0
0.75
0.75
0.9
0.9
0.9
0.9
1.1
1.1
0.9
0.9
1.25
1.25
1.5
1.5
Board
Termination
Voltage (V
TT
)
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
1.2
1.5
0.75
0.75
1.5
1.5
0.9
0.9
1.8
1.8
0.9
0.9
1.25
1.25
1.5
1.5
IOB
PAD4
Differential Pair
Switch
Matrix
IOB
PAD3
IOB
PAD2
Differential Pair
IOB
PAD1
DS031_30_101600
PCI66_3
PCI-X
GTL
GTLP
HSTL_I
HSTL_II
HSTL_III
HSTL_IV
HSTL_I_18
HSTL_II_18
HSTL_III _18
HSTL_IV_18
SSTL18_I
(2)
SSTL18_II
SSTL2_I
SSTL2_II
SSTL3_I
SSTL3_II
1.5 N/R
1.5 N/R
1.5 N/R
1.8 N/R
1.8 N/R
1.8
1.8
1.8
2.5
2.5
3.3
3.3
N/R
N/R
N/R
N/R
N/R
N/R
N/R
1.8 N/R
Figure 1: Virtex-II Input/Output Tile
Note: Differential I/Os must use the same clock.
Supported I/O Standards
Virtex-II IOB blocks feature SelectI/O-Ultra inputs and out-
puts that support a wide variety of I/O signaling standards.
In addition to the internal supply voltage (V
CCINT
=1.5V),
output driver supply voltage (V
CCO
) is dependent on the I/O
standard (see Table 1 and Table 2). An auxiliary supply volt-
age (V
CCAUX
= 3.3 V) is required, regardless of the I/O
standard used. For exact supply voltage absolute maximum
ratings, see DC Input and Output Levels in Module 3.
All of the user IOBs have fixed-clamp diodes to V
CCO
and to
AGP-2X/AGP3.3N/R1.32N/R
ground. As outputs, these IOBs are not compatible or com-
Notes:
pliant with 5V I/O standards. As inputs, these IOBs are not
1.V
CCO
of GTL or GTLP should not be lower than the termination
normally 5V tolerant, but can be used with 5V I/O standards
voltage or the voltage seen at the I/O pad. Example: If the pin High
level is 1.5V, connect V
CCO
to 1.5V.
when external current-limiting resistors are used. For more
18_I is not a JEDEC-supported standard.
details, see the “5V Tolerant I/Os“ Tech Topic.
3.N/R = no requirement.
Table 3 lists supported I/O standards with Digitally Con-
trolled Impedance. See Digitally Controlled Impedance
(DCI), page 8.
DS031-2 (v4.0) April 7, 2014
Product Specification
Virtex-II Platform FPGAs: Functional Description
Table 13: Virtex-II Logic Resources Available in All CLBs
CLB Array:
Row x
Column
8 x 8
16 x 8
24 x 16
32 x 24
40 x 32
48 x 40
56 x 48
64 x 56
80 x 72
96 x 88
112 x 104
Number Number
of of
SlicesLUTs
256
512
1,536
3,072
5,120
7,680
10,752
14,336
23,040
33,792
46,592
512
1,024
3,072
6,144
10,240
15,360
21,504
28,672
46,080
67,584
93,184
Max Distributed
SelectRAM or Shift
Register (bits)
8,192
16,384
49,152
98,304
163,840
245,760
344,064
458,752
737,280
1,081,344
1,490,944
Number
of
Flip-Flops
512
1,024
3,072
6,144
10,240
15,360
21,504
28,672
46,080
67,584
93,184
Number
of
Carry-Chains
(1)
16
16
32
48
64
80
96
112
144
176
208
Number
of SOP
Chains
(1)
16
32
48
64
80
96
112
128
160
192
224
Device
XC2V40
XC2V80
XC2V250
XC2V500
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
DS031-2 (v4.0) April 7, 2014
Product Specification
Virtex-II Platform FPGAs: Functional Description
Virtex-II FPGA device. Timing is similar to the Slave Serial-
MAP mode except that CCLK is supplied by the Virtex-II
FPGA.
IEEE 1532 standard for In-System Configurable (ISC)
devices. The IEEE 1532 standard is backward compliant
with the IEEE 1149.1-1993 TAP and state machine. The
IEEE Standard 1532 for In-System Configurable (ISC)
devices is intended to be programmed, reprogrammed, or
tested on the board via a physical and logical protocol.
Configuration through the Boundary-Scan port is always
available, independent of the mode selection. Selecting the
Boundary-Scan mode simply turns off the other modes.
Boundary-Scan (JTAG, IEEE 1532) Mode
In Boundary-Scan mode, dedicated pins are used for con-
figuring the Virtex-II device. The configuration is done
entirely through the IEEE 1149.1 Test Access Port (TAP).
Virtex-II device configuration using Boundary-Scan is com-
patible with the IEEE 1149.1-1993 standard and the new
Table
25: Virtex-II Configuration Mode Pin Settings
Configuration Mode
(1)
Master Serial
Slave Serial
Master SelectMAP
Slave SelectMAP
oundary-Scan
M2
0
1
0
1
1
M1
0
1
1
1
0
M0
0
1
1
0
1
CCLK Direction
Out
In
Out
In
N/A
Data Width
1
1
8
8
1
Serial D
OUT
(2)
Yes
Yes
No
No
No
DS031-2 (v4.0) April 7, 2014
Product Specification
Virtex-II Platform FPGAs: DC and Switching Characteristics
Table 5: Minimum Power On Current Required for Virtex-II Devices
Device (mA)
XC2V40, XC2V80,
XC2V250, XC2V500
I
CCINTMIN
I
CCAUXMIN
I
CCOMIN
200
100
50
XC2V1000
250
100
50
XC2V1500
350
100
100
XC2V2000
400
100
100
XC2V3000
500
100
100
XC2V4000
650
100
100
XC2V6000
800
100
100
XC2V8000
1100
100
100
Notes:
specified for power on current parameters are Commercial Grade. For Industrial Grade values, multiply Commercial Grade
values by 1.25.
2.I
CCOMIN
values listed here apply to the entire device (all banks).
General Power Supply Requirements
Proper decoupling of all FPGA power supplies is sessential.
Consult Xilinx Application Note
XAPP623
for detailed infor-
mation on power distribution system design.
V
CCAUX
powers critical resources in the FPGA. Thus,
V
CCAUX
is especially susceptible to power supply noise.
Changes in V
CCAUX
voltage outside of 200 mV peak to peak
should take place at a rate no faster than 10 mV per milli-
second. Techniques to help reduce jitter and period distor-
tion are provided in Xilinx Answer Record 13756.
V
CCAUX
can share a power plane with 3.3V V
CCO
, but only if
V
CCO
does not have excessive noise. Using simultaneously
switching output (SSO) limits are essential for keeping
power supply noise to a minimum. Refer to
XAPP689
, “Man-
aging Ground Bounce in Large FPGAs,” to determine the
number of simultaneously switching outputs allowed per
bank at the package level.
DC Input and Output Levels
Values for V
IL
and V
IH
are recommended input voltages.
Values for I
OL
and I
OH
are guaranteed over the recom-
mended operating conditions at the V
OL
and V
OH
test
points. Only selected standards are tested. These are cho-
Table 6: DC Input and Output Levels
Input/Output
Standard
LVTTL
(1)
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
PCI33_3
PCI66_3
PCI–X
GTLP
GTL
HSTL I
HSTL II
HSTL III
HSTL IV
sen to ensure that all standards meet their specifications.
The selected standards are tested at minimum V
CCO
with
the respective V
OL
and V
OH
voltage levels shown. Other
standards are sample tested.
V
IL
V, Min
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
V
IH
V, Min
2.0
2.0
1.7
65% V
CCO
65% V
CCO
50% V
CCO
50% V
CCO
Note 2
V
REF
+ 0.1
V
REF
+ 0.05
V
REF
+ 0.1
V
REF
+ 0.1
V
REF
+ 0.1
V
REF
+ 0.1
V
OL
V, Max
3.6
3.6
2.7
1.95
1.7
V
CCO
+ 0.5
V
CCO
+ 0.5
Note 2
V
CCO
+ 0.5
V
CCO
+ 0.5
V
CCO
+ 0.5
V
CCO
+ 0.5
V
CCO
+ 0.5
V
CCO
+ 0.5
V
OH
V, Min
2.4
V
CCO
–0.4
V
CCO
–0.4
V
CCO
–0.4
V
CCO
–0.4
90% V
CCO
90% V
CCO
Note 2
n/a
n/a
V
CCO
–0.4
V
CCO
–0.4
V
CCO
–0.4
V
CCO
–0.4
I
OL
mA
24
24
24
16
16
Note 2
Note 2
Note 2
36
40
8
16
24
48
I
OH
mA
–24
–24
–24
–16
–16
Note 2
Note 2
Note 2
n/a
n/a
–8
–16
–8
–8
V, Max
0.8
0.8
0.7
35% V
CCO
35% V
CCO
30% V
CCO
30% V
CCO
Note 2
V
REF
–0.1
V
REF
–0.05
V
REF
–0.1
V
REF
–0.1
V
REF
–0.1
V
REF
–0.1
V, Max
0.4
0.4
0.4
0.4
0.4
10% V
CCO
10% V
CCO
Note 2
0.6
0.4
0.4
0.4
0.4
0.4
DS031-3 (v4.0) April 7, 2014
Product Specification
Virtex-II Platform FPGAs: DC and Switching Characteristics
Table 6: DC Input and Output Levels (Continued)
Input/Output
Standard
SSTL3 I
SSTL3 II
SSTL2 I
SSTL2 II
AGP
V
IL
V, Min
–0.5
–0.5
–0.5
–0.5
–0.5
V
IH
V, Min
V
REF
+ 0.2
V
REF
+ 0.2
V
REF
+ 0.15
V
REF
+ 0.15
V
REF
+ 0.2
V
OL
V, Max
V
CCO
+ 0.5
V
CCO
+ 0.5
V
CCO
+ 0.5
V
CCO
+ 0.5
V
CCO
+ 0.5
V
OH
V, Min
V
REF
+ 0.6
V
REF
+ 0.8
V
REF
+ 0.65
V
REF
+ 0.80
90% V
CCO
I
OL
mA
8
16
7.6
15.2
Note 2
I
OH
mA
–8
–16
–7.6
–15.2
Note 2
V, Max
V
REF
–0.2
V
REF
–0.2
V
REF
–0.15
V
REF
–0.15
V
REF
–0.2
V, Max
V
REF
–0.6
V
REF
–0.8
V
REF
–0.65
V
REF
–0.80
10% V
CCO
Notes:
1.V
OL
and V
OH
for lower drive currents are sample tested. The DONE pin is always LVTTL 12 mA.
according to the relevant specifications.
and LVCMOS inputs have approximately 100 mV of hysteresis.
DS031-3 (v4.0) April 7, 2014
Product Specification