ADV7480是一款组合式HDMI和MHL接收器,MIPI-CSI 输出或8bit数字信号输出-USB迷|专注于互联网分享

2024年10月13日发(作者：宗勇锐)

Data Sheet

Dual Mode HDMI/MHL Receiver

ADV7480

HDMI/MHL audio extraction support

Advanced audio muting feature

S-compatible, left justified and right justified audio

output modes

8-channel TDM output mode available

Mobile Industry Processor Interface (MIPI) Camera Serial

Interface 2 (CSI-2) transmitter

4-lane transmitter with 4 lanes, 2 lanes, and 1 lane muxing

options for HDMI/MHL/digital input port sources

8-bit digital input/output port

General

2-wire serial microprocessor unit (MPU) interface (I

compatible)

−40°C to +85°C temperature grade

100-ball, 9 mm × 9 mm, RoHS-compliant CSP_BGA package

Qualified for automotive applications

FEATURES

Mobile High-Definition Link (MHL) capable receiver

High-bandwidth Digital Content Protection (HDCP)

authentication and decryption support

75 MHz maximum pixel clock frequency, allowing HDTV

formats up to 720p/1080i at 60 Hz

24 bits per pixel mode supported

HDCP repeater support, up to 25 KSVs supported

Adaptive TMDS equalizer

High-Definition Multimedia Interface (HDMI) capable

receiver

HDCP authentication and decryption support

162 MHz maximum pixel clock frequency, allowing HDTV

formats up to 1080p and display resolutions up to UXGA

(1600 × 1200 at 60 Hz)

HDCP repeater support, up to 25 KSVs supported

Integrated CEC controller, CEC 1.4 compatible

Adaptive TMDS equalizer

5 V detect and Hot Plug assert

Component video processor

Any-to-any 3 × 3 color space conversion (CSC) matrix

Contrast/brightness/hue/saturation video adjustment

Timing adjustments controls for horizontal sync

(HS)/vertical sync (VS)/data enable (DE) timing

Video mute function

Serial digital audio output interface

APPLICATIONS

Portable devices

Automotive infotainment (head unit and rear seat

entertainment systems)

HDMI repeaters and video switches

FUNCTIONAL BLOCK DIAGRAM

ADV7480

RXCP/RXCN

RX0P/RX0N

RX1P/RX1N

RX2P/RX2N

DDC_SCL/

CD_PULLUP

DDC_SDA

HPD/CBUS

CD_SENSE

CEC

RX_5V/VBUS

VBUS_EN

LLC

P0TO P7

SPI

SLAVE

SPI_MISO

SPI_MOSI

SPI_SCLK

SPI_CS

ALSB

SCLK

SDATA

INTRQ1TO

INTRQ3

I2S_MCLK

I2S_LRCLK

I2S_SCLK

I2S_SDATA

CLKAP/CLKAN

DA0P/DA0NTO

DA3P/DA3N

MHL_SENSE

CBUS

DDC

HDMI/MHL

RECEIVER

AUDIO

PROCESSOR

CEC

HPD

EDID RAM

HDCP

8-BIT TTL

INPUT/OUTPUT

COMPONENT

PROCESSOR

(CP)

SLAVE

INTERRUPTS

CONTROLLER

AUDIO

OUTPUT

FORMATTER

4-LANE

MIPI CSI-2

TRANSMITTER

Figure 1.

Rev. 0

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

ADV7480

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

General Description ......................................................................... 3

Detailed Functional Block Diagram .............................................. 4

Specifications ..................................................................................... 5

Electrical Characteristics ............................................................. 5

MIPI Video Output Specifications ............................................. 7

Timing Specifications .................................................................. 8

Absolute Maximum Ratings .......................................................... 12

Thermal Resistance .................................................................... 12

ESD Caution ................................................................................ 12

Pin Configuration and Function Descriptions ........................... 13

Power . 16

Data Sheet

Power-Up Sequence ................................................................... 16

Power-Down Sequence .............................................................. 16

Theory of Operation ...................................................................... 17

Combined HDMI/MHL Receiver ............................................ 17

MHL Receiver ............................................................................. 17

HDMI Receiver ........................................................................... 17

Component Processor ............................................................... 18

8-Bit Digital Input/Output Port ............................................... 18

Audio Processing ........................................................................ 18

MIPI CSI-2 Transmitter ............................................................ 18

Interrupts ..................................................................................... 18

Outline Dimensions ...................................................................... 19

Ordering Guide .......................................................................... 19

Automotive Products ................................................................. 19

REVISION HISTORY

6/14—Revision 0: Initial Version

Rev. 0 | Page 2 of 19

Data Sheet

ADV7480

The ADV7480 contains a component processor (CP) that

processes the video signals from the HDMI/MHL receiver. It

provides features such as contrast, brightness, and saturation

adjustments, as well as free run and timing adjustment controls

for HS/VS/DE timing.

The ADV7480 features an 8-bit digital input/output port,

supporting input and output video resolutions up to 720p/1080i

in both the 8-bit interleaved 4:2:2 SDR and DDR modes.

To enable glueless interfacing of these video input sources to the

latest generation of infotainment system on chips (SoCs), the

ADV7480 features a MIPI® CSI-2 transmitter. The four-lane

transmitter provides four data lanes, two data lanes, and one

data lane muxing options, and can be used to output video from

the HDMI receiver, the MHL receiver, and the digital input

port.

The ADV7480 offers a flexible audio output port for audio data

extracted from the MHL or HDMI streams. The HDMI/MHL

receiver has advanced audio functionality, such as a mute

controller that prevents audible extraneous noise in the audio

output. Additionally, the ADV7480 can be set to output time

division multiplexing (TDM) serial audio, which allows the

transmission of eight multiplexed serial audio channels on a

single audio output interface port.

The ADV7480 is programmed via a 2-wire, serial, bidirectional

port (I

C compatible).

Fabricated in an advanced CMOS process, the ADV7480 is

available in a 9 mm × 9 mm, RoHS-compliant, 100-ball

CSP_BGA package and is specified over the −40°C to +85°C

temperature range.

The ADV7480 is offered in automotive and industrial versions.

GENERAL DESCRIPTION

The ADV7480 is a combined HDMI®/MHL® receiver targeted at

connectivity enabled head units requiring a wired, uncompressed

digital audio/video link from smartphones and other consumer

electronics devices to support streaming and integration of

cloud-based multimedia content and applications into an

automotive infotainment system.

The ADV7480 MHL 2.1 capable receiver supports a maximum

pixel clock frequency of 75 MHz, allowing resolutions up to

720p/1080i at 60 Hz in 24-bit mode. The ADV7480 features a

link control bus (CBUS) that handles the link layer, translation

layer, CBUS electrical discovery, and display data channel

(DDC) commands. The implementation of the MHL sideband

channel (MSC) commands by the system processor can be

handled either by the I

C bus, or via a dedicated serial

peripheral interface (SPI) bus. A dedicated interrupt pin

(INTRQ3) is available to indicate that events related to CBUS

have occurred.

The ADV7480 also features an enable pin (VBUS_EN) to

dynamically enable or disable the output of a voltage regulator,

which provides a 5 V voltage bus (VBUS) signal to the MHL

source.

The ADV7480 HDMI capable receiver supports a maximum

pixel clock frequency of 162 MHz, allowing HDTV formats up

to 1080p, and display resolutions up to UXGA (1600 × 1200 at

60 Hz). The device integrates a consumer electronics control

(CEC) controller that supports the capability discovery and

control (CDC) feature. The HDMI input port has dedicated 5 V

detect and Hot Plug™ assert pins.

The HDMI/MHL receiver includes an adaptive transition

minimized differential signaling (TMDS) equalizer that ensures

robust operation of the interface with long cables.

The ADV7480 single receiver port is capable of accepting both

HDMI and MHL electrical signals. Automatic detection

between HDMI and MHL is achieved by using cable impedance

detection through the CD_SENSE pin.

Rev. 0 | Page 3 of 19

ADV7480

Data Sheet

DETAILED FUNCTIONAL BLOCK DIAGRAM

XTALP

XTALN

SCLK

SDATA

ALSB

RESET

SPI_MISO

SPI_MOSI

SPI_SCLK

SPI_CS

CLOCK

PROCESSING

BLOCK

C SLAVE/

CONTROL

ADV7480

SPI

SLAVE

CBUS

CONTROLLER

GENERAL

INTERRUPTS

CONTROLLER

CBUS

INTERRUPTS

CONTROLLER

INTRQ1

INTRQ2

INTRQ3

VBUS_EN

CD_SENSE

HPD/CBUS

RX_5V/VBUS

CEC

DDC_SDA

DDC_SCL/

CD_PULLUP

RXCP/RXCN

RX0P/RX0N

RX1P/RX1N

RX2P/RX2N

LLC

MHL LINK

DISCOVERY

BLOCK

5V DETECTAND

HPD PIN

CONTROLLER

CEC

CONTROLLER

EDID/

REPEATER

CONTROLLER

HDCP

KEYS

HDCP

ENGINE

PACKET/

INFOFRAME

MEMORY

PACKET

PROCESSOR

AUDIO

PROCESSOR

AUDIO OUTPUT

FORMATTER

I2S_MCLK

I2S_LRCLK

I2S_SCLK

I2S_SDATA

PLL

EQUALIZER

SAMPLER

HDMI/MHL

PROCESSOR

COLOR

SPACE

CONVERSION

COMPONENT

PROCESSOR

(CP)

8-BIT

6-BIT

DITHER

BLOCK

MIPI CSI-2

TRANSMITTER A

CLKAP/CLKAN

DA0P/DA0N

DA1P/DA1N

DA2P/DA2N

DA3P/DA3N

CSI-2 Tx

8-BIT

DIGITAL

INPUT/

OUTPUT

PORT

D-PHY Tx

Figure 2.

Rev. 0 | Page 4 of 19

Data Sheet

ADV7480

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

AVDD = 1.71 V to 1.89 V, DVDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, MVDD = 1.71 V to 1.89 V, CVDD = 1.71 V to 1.89 V,

DVDDIO = 3.14 V to 3.46 V, and TVDD = 3.14 V to 3.46 V, specified at operating temperature range, unless otherwise noted.

Table 1.

Parameter

DIGITAL INPUTS

Input High Voltage

Input Low Voltage

Input Leakage Current

Input Capacitance

CRYSTAL INPUT

Input High Voltage

Input Low Voltage

DIGITAL OUTPUTS

Symbol

Test Conditions/Comments

SCLK, SDATA, RESET, ALSB, SPI_CS, SPI_SCLK,

SPI_MOSI, LLC, and P0 to P7

DVDDIO = 3.14 V to 3.46 V

XTALP

LLC, P0 to P7, I2S_MCLK, I2S_SCLK, I2S_LRCLK,

I2S_SDATA, SPI_MISO, SDATA, INTRQ1 to INTRQ3

(when configured to drive when active), and

VBUS_EN

DVDDIO = 3.14 V to 3.46 V and I

SOURCE

= 0.4 mA

DVDDIO = 3.14 V to 3.46 V and I

SINK

= 3.2 mA

3.3 V operation

Rev. 0 | Page 5 of 19

Min

−10

1.2

Typ

Max

0.8

+10

0.4

Unit

µA

Output High Voltage

Output Low Voltage

High Impedance Leakage Current

Output Capacitance

POWER REQUIREMENTS

Digital Power Supply

HDMI/MHL Terminator Supply

HDMI/MHL Comparator Supply

PLL Power Supply

MIPI Transmitter Power Supply

Digital Input/Output Power Supply

Analog Power Supply

CURRENT CONSUMPTION

1, 2, 3, 4

Digital Supply Current

HDMI Input

MHL Input

8-Bit Digital Input

HDMI/MHL Terminator Supply Current

HDMI Input

MHL Input

8-Bit Digital Input

HDMI/MHL Comparator Supply Current

HDMI Input

MHL Input

8-Bit Digital Input

PLL Supply Current

HDMI Input

MHL Input

8-Bit Digital Input

MIPI Transmitters Supply Current

HDMI Input

MHL Input

8-Bit Digital Input

LEAK

OUT

VDD

VDDIO

VDD

DVDD

TVDD

CVDD

PVDD

MVDD

2.4

1.71

3.14

1.71

3.14

1.71

1.8

3.3

1.8

3.3

1.8

68.1

93.5

32.5

24.4

0.7

63.9

55.9

0.1

29.2

29.3

27.9

45.7

38.5

38.1

0.4

1.89

3.46

1.89

3.46

1.89

204

µA

ADV7480

Data Sheet

Symbol

DVDDIO

AVDD

DVDD_PD

TVDD_PD

CVDD_PD

PVDD_PD

MVDD_PD

DVDDIO_PD

AVDD_PD

Test Conditions/Comments

Min

Typ

3.6

0.6

0.2

0.1

0.2

0.4

0.1

0.2

0.1

Max

Unit

Parameter

Digital Input/Output Supply Current

HDMI Input

MHL Input

8-Bit Digital Input

Analog Supply Current

HDMI Input

MHL Input

8-Bit Digital Input

POWER-DOWN CURRENTS

2, 5

Digital Supply

HDMI/MHL Terminator Supply

HDMI/MHL Comparator Supply

PLL Supply

MIPI Transmitter Supply

Digital Input/Output Supply

Analog Supply

Total Power Dissipation in Power-Down

Mode

Guaranteed by lab characterization.

Typical current consumption values are recorded with nominal voltage supply levels (including DVDDIO = 3.3 V), Philips test pattern, and at room temperature.

Maximum current consumption values are recorded with maximum rated voltage supply levels (including DVDDIO = 3.46 V), pseudorandom test pattern for digital

inputs, and at worst-case temperature.

Typical power-down current consumption values are recorded with nominal voltage supply levels (including DVDDIO = 3.3 V) at room temperature.

The 8-bit digital input/output port is only available when the DVDDIO supply is between 3.14 V and 3.46 V

Rev. 0 | Page 6 of 19

Data Sheet

ADV7480

MIPI VIDEO OUTPUT SPECIFICATIONS

AVDD = 1.71 V to 1.89 V, DVDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, MVDD = 1.71 V to 1.89 V, CVDD = 1.71 V to 1.89 V,

DVDDIO = 3.14 V to 3.46 V, and TVDD = 3.14 V to 3.46 V, specified at operating temperature range, unless otherwise noted.

The ADV7480 MIPI CSI-2 transmitter conforms to the MIPI D-PHY Version 1.00.00 specification by characterization. The clock lane of

the ADV7480 remains in high speed (HS) mode even when the data lane enters low power (LP) mode. For this reason, some

measurements on the clock lane that pertain to low power mode are not applicable. Unless otherwise stated, all high speed measurements

were performed with the ADV7480 operating with a nominal 1 Gbps output data rate.

Table 2.

Parameter

UNIT INTERVAL

DATA LANE LP Tx DC SPECIFICATIONS

Thevenin Output

High Level

Low Level

CLOCK LANE LP Tx DC SPECIFICATIONS

Thevenin Output

High Level

Low Level

DATA LANE HS Tx SIGNALING REQUIREMENTS

High Speed Differential Voltage Swing

Differential Voltage Mismatch

Single-Ended Output High Voltages

Static Common-Mode Voltage Level

CLOCK LANE HS Tx SIGNALING REQUIREMENTS

High Speed Differential Voltage Swing

Differential Voltage Mismatch

Single-Ended Output High Voltages

Static Common-Mode Voltage Level

HS Tx CLOCK TO DATA LANE TIMING REQUIREMENTS

Data to Clock Skew

Symbol

Min

1.1

−50

1.1

−50

140

150

140

150

0.35 × UI

Typ

1.2

200

Max

12.5

1.3

+50

1.3

+50

270

360

250

270

360

250

0.65 × UI

Unit

mV p-p

Guaranteed by design.

These measurements were performed with C

LOAD

= 50 pF.

Rev. 0 | Page 7 of 19

ADV7480

Data Sheet

TIMING SPECIFICATIONS

AVDD = 1.71 V to 1.89 V, DVDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, MVDD = 1.71 V to 1.89 V, CVDD = 1.71 V to 1.89 V,

DVDDIO = 3.14 V to 3.46 V, and TVDD = 3.14 V to 3.46 V, specified at operating temperature range, unless otherwise noted.

Table 3.

Parameter

CLOCK AND CRYSTAL

Nominal Frequency

Frequency Stability

Input LLC Clock Frequency Range

2,3

Output LLC Clock Frequency Range

2,3

SPI_SCLK Frequency

I2S_SCLK Frequency

I2S_MCLK Frequency

C PORT

SCLK Frequency

SCLK Minimum Pulse Width High

SCLK Minimum Pulse Width Low

Hold Time (Start Condition)

Setup Time (Start Condition)

SDATA Setup Time

SCLK and SDATA Rise Times

SCLK and SDATA Fall Times

Setup Time (Stop Condition)

SPI PORT

Slave Mode

SPI_CS Falling Edge to SPI_SCLK

Active Edge

SPI_SCLK Active Edge to SPI_CS

Rising Edge

SPI_CS Pulse Width

SPI_SCLK High Time

SPI_SCLK Low Time

SPI_MOSI Setup Time

SPI_MOSI Hold Time

SPI_SCLK Falling Edge to SPI_MISO

Start of Data Invalid

SPI_SCLK Falling Edge to SPI_MISO

End of Data Invalid

SPI_MOSI Setup Time

SPI_MOSI Hold Time

SPI_SCLK Rising Edge to SPI_MISO

Start of Data Invalid

SPI_SCLK Rising Edge to SPI_MISO

End of Data Invalid

RESET FEATURE

RESET Pulse Width

Symbol

Test Conditions/Comments

DVDDIO = 3.14 V to 3.46 V

SPI_SCLK active edge (rising or falling

edge) depends on the values of CPHA

and CPOL

SPI_SCLK active edge (rising or falling

edge) depends on the values of CPHA

and CPOL

SPI Mode 0, SPI Mode 3

SPI Mode 1, SPI Mode 2

Min

13.5

0.6

1.3

0.6

100

Typ

28.63636

0.6

Max

±50

148.5

12.288

24.576

400

300

Unit

MHz

ppm

MHz

kHz

µs

% duty

cycle

% duty

cycle

Rev. 0 | Page 8 of 19

Data Sheet

ADV7480

Symbol Test Conditions/Comments

DVDDIO = 3.14 V to 3.46 V

Data latched on rising edge

Data latched on falling edge

DVDDIO = 3.14 V to 3.46 V

At P0 to P7 output pin, data latched

on rising edge

At P0 to P7 output pin, data latched

on rising edge

At P0 to P7 output pin, data latched

on rising edge

At P0 to P7 output pin, data latched

on rising edge

At P0 to P7 output pin, data latched

on falling edge

At P0 to P7 output pin, data latched

on falling edge

End of valid data to I2S_SCLK falling

edge

I2S_SCLK falling edge to start of valid

data

End of valid data to I2S_SCLK falling

edge

I2S_SCLK falling edge to start of valid

data

Min

1.98

2.50

1.66

3.52

1.71

3.17

Typ

Max

Unit

% duty

cycle

% duty

cycle

% duty

cycle

% duty

cycle

% duty

cycle

% duty

cycle

Parameter

8-BIT DIGITAL INPUT PORT

LLC High Time

LLC Low Time

SDR and DDR Modes Setup Time

SDR and DDR Modes Hold Time

DDR Mode Setup Time

DDR Mode Hold Time

8-BIT DIGITAL OUTPUT PORT

LLC High Time

LLC Low Time

SDR Modes Setup Time

4, 5

SDR Modes Hold Time

4, 5

DDR Modes Setup Time

4, 5

DDR Modes Hold Time

4, 5

DDR Mode Setup Time

4, 5

DDR Modes Hold Time

4, 5

S PORT, MASTER MODE

I2S_SCLK High Time

I2S_SCLK Low Time

I2S_LRCLK Data Transition Time

I2S_SDATA Data Transition Time

Required by design.

The 8-bit digital input/output port is only available when the DVDDIO supply is between 3.14 V and 3.46 V.

Guaranteed by design.

These specifications only apply when the LLC_DLL_PHASE[4:0] (IO Map, Register 0x0C[4:0]) is set to 00000

Guaranteed by lab characterization.

Rev. 0 | Page 9 of 19

ADV7480

Data Sheet

SDATA

Timing Diagrams

SCLK

Figure 3. I

C Timing

SPI

MODE

CPOLCPHA

SPI_CS

SPI_SCLK

W/R

DEVICE ADDRESS

SPI_MOSI

7654321076

SUBADDRESS

54321076

DATA IN 0

54321076

DATA IN 1

543210

DUMMY BYTEDATA OUT 0

76543210

DELAY MODE 1

SPI_MISO

DATA OUT 0

DELAY MODE 0

SPI_MISO

76543210

DATA OUT 1

76543210

Figure 4. Detailed SPI Slave Timing Diagram

SPI_SCLK

SPI_MOSI

SPI_CS

SPI_MISO

Figure 5. SPI Slave Mode Timing (SPI Mode 0 and SPI Mode 3)

SPI_SCLK

SPI_MOSI

SPI_CS

SPI_MISO

Figure 6. SPI Slave Mode Timing (SPI Mode 1 and SPI Mode 2)

Rev. 0 | Page 10 of 19

Data Sheet

LLC

ADV7480

P[7:0]

Figure 7. 8-Bit Digital Pixel Video Input, SDR Video Data Timing

LLC

P[7:0]

Figure 8. 8-Bit Digital Pixel Video Input, DDR Video Data Timing

LLC

P7TO P0

Figure 9. 8-Bit Digital Pixel Video Output, SDR Video Data Timing

LLC

P7TO P0

Figure 10. 8-Bit Digital Pixel Video Output, DDR Video Data Timing

I2S_SCLK

I2S_LRCLK

I2S_SDATA

LEFT-JUSTIFIED

MODE

MSBMSB – 1

I2S_SDATA

SMODE

MSB

MSB – 1

I2S_SDATA

RIGHT-JUSTIFIED

MODE

MSB

LSB

Figure 11. I2S Timing

Rev. 0 | Page 11 of 19

ADV7480

Data Sheet

THERMAL RESISTANCE

Rating

4 V

2.2 V

−0.3 V to +0.3 V

GND − 0.3 V to DVDDIO +

0.3 V

GND − 0.3 V to DVDDIO +

0.3 V

−0.3 V to AVDD + 0.3 V

−0.3 V to PVDD + 0.3 V

−0.3 V to CVDD + 0.3 V

−0.3 V to +5.5 V

125°C

−65°C to +150°C

260°C

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter

TVDD, DVDDIO to GND

AVDD, PVDD, MVDD, DVDD, CVDD

to GND

CVDD to DVDD

MVDD to DVDD

PVDD to DVDD

AVDD to DVDD

Digital Inputs Voltage to GND

Digital Outputs Voltage to GND

Analog Inputs to GND

XTALN and XTALP to GND

HDMI/MHL Digital Inputs Voltage

to GND

5 V Tolerant Inputs Voltage to

GND

Maximum Junction Temperature

max)

Storage Temperature Range

Infrared Reflow Soldering

(20 sec)

To reduce power consumption when using the ADV7480, turn

off unused sections of the device.

Due to printed circuit board (PCB) metal variation, and,

therefore, variation in PCB heat conductivity, the value of θ

may differ for various PCBs.

The most efficient measurement solution is achieved using the

package surface temperature to estimate the die temperature.

This eliminates the variance associated with the θ

value.

Do not exceed the maximum junction temperature (T

max) of

125°C. The following equation calculates the junction

temperature (T

) using the measured package surface

temperature and applies only when no heat sink is used on the

device under test (DUT):

= T

+ (Ψ

×W

TOTAL

)

where:

is the package surface temperature (°C).

= 0.81°C/W for the 100-ball CSP_BGA (based on 2s2p test

board defined by JEDEC standards.

TOTAL

= (PVDD × I

PVDD

) + (TVDD × I

TVDD

) − P

UpStream

(CVDD × I

CVDD

) + (AVDD × I

AVDD

) + (DVDD × I

DVDD

) +

(DVDDIO × I

DVDDIO

) + (MVDD × I

MVDD

)

where P

UpStream

is the quantity of TVDD power consumed on the

upstream HDMI or MHL transmitter. P

UpStream

can be estimated

to be around 110 mW for a nominal HDMI transmitter. P

UpStream

can be estimated to be around 42.82 mW for a nominal MHL

transmitter.

The following inputs are 3.3 V inputs but are 5 V tolerant:

DDC_SCL/CD_PULLUP, DDC_SDA, HPD/CBUS, RX_5V/VBUS, CD_SENSE, and

CEC.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

ESD CAUTION

Rev. 0 | Page 12 of 19

Data Sheet

ADV7480

AGND

I2S_

SDATA

I2S_

SCLK

GND

RX2P

RX1P

RX0P

RXCP

8910

GNDA

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DDC_SCL/

CD_

VBUS_EN

PULLUP

MVDDCVDDRX2NRX1NRX0NRXCN

DDC_SDA

HPD/

CBUS

DNC

GND

CLKANCLKAP

I2S_

LRCLK

I2S_

MCLK

CD_

SENSE

TVDD

CEC

RX_5V/

VBUS

DNC

DA0NDA0PINTRQ3DVDDGNDGNDGNDDNCDNCDNC

DA1NDA1PINTRQ2GNDGNDGNDAVDDDNCDNCDNC

DA2NDA2PINTRQ1GNDGNDGNDGNDDNCDNCDNC

DA3NDA3PTESTDVDDGNDGNDGNDDNCDNCDNC

DNCDNCDVDDIOP1P4

SPI_MOSI

SPI_CSRESETPVDDGND

DNCDNCMVDDP2P5P7

SPI_MISO

SCLKXTALNXTALP

GND

MVDD

LLC

SPI_SCLK

SDATA

ALSB

GND

DNC = DO NOT CONNECT. LEAVE THIS PIN UNCONNECTED.

Figure 12. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

A10

B10

Mnemonic

GND

I2S_SDATA

GND

RX2P

RX1P

RX0P

RXCP

DDC_SCL/CD_PULLUP

VBUS_EN

GND

MVDD

I2S_SCLK

CVDD

RX2N

RX1N

RX0N

RXCN

DDC_SDA

HPD/CBUS

GND

Type

Ground

Output

Ground

HDMI

HDMI/MHL

HDMI

HDMI/MHL

MHL

Ground

Power

Output

Power

HDMI

HDMI/MHL

HDMI

HDMI/MHL

Ground

Description

Ground.

S Audio Output.

Ground.

HDMI Digital Input Channel 2.

HDMI Digital Input Channel 1.

HDMI Digital Input Channel 0 or MHL TMDS+.

HDMI Input Clock.

HDCP Slave Serial Clock or MHL Cable Detect Pull-Up.

Enable Control Signal for Voltage Regulator Providing a 5 V VBUS

Supply.

Ground.

MIPI Supply Voltage (1.8 V).

Audio Serial Clock.

HDMI/MHL Comparator Supply Voltage (1.8 V). This is the supply

for the HDMI/MHL sensitive analog circuitry. Blocks on this supply

include the TMDS PLL and the equalizers.

HDMI Digital Input Channel 2 Complement.

HDMI Digital Input Channel 1 Complement.

HDMI Digital Input Channel 0 Complement or MHL TMDS−.

HDMI Input Clock Complement.

HDCP Slave Serial Data.

HDMI Hot Plug Assert or MHL CBUS.

Ground.

Rev. 0 | Page 13 of 19

ADV7480

Data Sheet

Type

Output

MHL

Power

HDMI

HDMI/MHL

Miscellaneous

Output

Power

Ground

Miscellaneous

Output

Ground

Power

Miscellaneous

Output

Ground

Miscellaneous

Output

Miscellaneous

Power

Ground

Miscellaneous

Description

MIPI Transmitter A Negative Output Clock.

MIPI Transmitter A Positive Output Clock.

Audio Left/Right Clock.

Audio Master Clock Output.

MHL Cable Detection Sense Input.

HDMI/MHL Terminator Supply Voltage (3.3 V).

CEC Channel.

HDMI 5 V Detect or MHL VBUS. A large pull-down resistor (100 kΩ,

typical) to ground must be connected to this pin.

Do Not Connect. Leave this pin unconnected.

MIPI Transmitter A Negative Data Output.

MIPI Transmitter A Positive Data Output.

Interrupt Request Output.

Digital Supply Voltage (1.8 V).

Ground.

Do Not Connect. Leave this pin unconnected.

MIPI Transmitter A Negative Data Output.

MIPI Transmitter A Positive Data Output.

Interrupt Request Output.

Ground.

Analog Supply Voltage (1.8 V).

Do Not Connect. Leave this pin unconnected.

MIPI Transmitter A Negative Data Output.

MIPI Transmitter A Positive Data Output.

Interrupt Request Output.

Ground.

Do Not Connect. Leave this pin unconnected.

MIPI Transmitter A Negative Data Output.

MIPI Transmitter A Positive Data Output.

Do Not Connect. Leave this pin unconnected.

Digital Supply Voltage (1.8 V).

Ground.

Do Not Connect. Leave this pin unconnected.

Pin No.

C10

D10

E10

F10

G10

Mnemonic

CLKAN

CLKAP

I2S_LRCLK

I2S_MCLK

CD_SENSE

TVDD

CEC

RX_5V/VBUS

DNC

DA0N

DA0P

INTRQ3

DVDD

GND

DNC

DA1N

DA1P

INTRQ2

GND

AVDD

DNC

DA2N

DA2P

INTRQ1

GND

DNC

DA3N

DA3P

TEST

DVDD

GND

DNC

Rev. 0 | Page 14 of 19

Data Sheet

ADV7480

Type

Miscellaneous

Power

Input/Output

Input

Power

Ground

Miscellaneous

Power

Input/Output

Output

Input

Output

Description

Do Not Connect. Leave this pin unconnected.

Digital Input/Output Supply Voltage (3.3 V).

Video Pixel Input/Output Port.

SPI Slave Data Input.

SPI Slave Chip Select Input.

System Reset Input, Active Low. A minimum low reset pulse of

5 ms is required to reset the chip.

PLL Supply Voltage (1.8 V).

Ground.

Do Not Connect. Leave this pin unconnected.

MIPI Supply Voltage (1.8 V).

Video Pixel Input/Output Port.

SPI Slave Data Output.

C Port Serial Clock Input.

Crystal Output. This pin must be connected to the 28.63636 MHz

crystal or not connected if an external 1.8 V, 28.63636 MHz clock

oscillator is used. In crystal mode, the crystal must be a

fundamental crystal.

Crystal Input or External Clock Input. This pin must be connected

to the 28.63636 MHz crystal or connected to an external 1.8 V,

28.63636 MHz clock oscillator if a clock oscillator is used. In crystal

mode, the crystal must be a fundamental crystal.

Ground.

MIPI Supply Voltage (1.8 V).

Video Pixel Input/Output Port.

Line Locked Clock. Input/output clock for the pixel data.

SPI Slave Clock Input.

C Port Serial Data Input/Output.

Main I

C Address Selection Pin. This pin selects the main I

address (IO Map I

C address) for the device. When ALSB is set to

Logic 0, the IO Map I

C write address is 0xE0; when ALSB is set to

Logic 1, the IO Map I

C write address is 0xE2.

Ground.

Pin No.

H10

Mnemonic

DNC

DVDDIO

SPI_MOSI

SPI_CS

RESET

PVDD

GND

DNC

MVDD

SPI_MISO

SCLK

XTALN

J10 XTALP Input

GND

MVDD

LLC

SPI_SCLK

SDATA

ALSB

Ground

Power

Input/Output

Input

Input/Output

Input

K10 GND Ground

Rev. 0 | Page 15 of 19

ADV7480

Data Sheet

POWER-DOWN SEQUENCE

The ADV7480 power supplies can be deasserted simultaneously

as long as a higher rated supply (for example, D

VDDIO

) does not

fall to a voltage level less than a lower rated supply (for example,

VDD

), and the absolute maximum ratings specifications are

followed.

POWER SUPPLY RECOMMENDATION

POWER-UP SEQUENCE

Adhere to the absolute maximum ratings at all times during

power-up (see Table 4). The power-up sequence for the

ADV7480 is as follows:

1. Assert

RESET

(pull the pin low).

2. Power up the 3.3 V supplies (D

VDDIO

and T

VDD

). These

supplies must be powered up simultaneously.

3. Power up the 1.8 V supplies (D

VDD

, C

VDD

, P

VDD

, M

VDD

, and

VDD

). These supplies must be powered up simultaneously.

RESET

can be deasserted (pulled high) 5 ms after all

supplies are fully powered up.

5. After all power supplies and the

RESET

pin are powered up

and stable, wait an additional 5 ms before initiating I

communication with the ADV7480.

3.3V

RESET

3.3V

3.3V SUPPLIES

1.8V

1.8V SUPPLIES

RESET > 5ms

Figure 13. Supply Power-Up Sequence

Rev. 0 | Page 16 of 19

Data Sheet

ADV7480

The implementation of the MSC commands by the system

processor can be handled either through the I

C bus, or via a

dedicated SPI bus. A dedicated interrupt pin (INTRQ3) is

available to indicate that events related to the CBUS have occurred.

The main MHL receiver features include

• Support for a pixel clock up to 75 MHz in 24-bit mode,

allowing support for video formats up to 720p/1080i and

display resolutions up to XGA in either RGB, YCbCr 4:4:4,

or YCbCr 4:2:2 formats.

Integrated fully adaptive equalizer for cable lengths up to

2 meters.

HDCP 1.4 support.

Internal HDCP keys.

HDCP repeater support, up to 25 key selection vectors

(KSVs) supported.

Pulse code modulation (PCM) audio packet support.

Support for 8-channel TDM output data up to 48 kHz.

Repeater support.

Internal EDID RAM (512-byte for single mode, and

256-byte for dual mode operation).

Scratchpad register support with a size of 64 bytes.

THEORY OF OPERATION

COMBINED HDMI/MHL RECEIVER

The ADV7480 features a combined HDMI/MHL receiver. This

single receiver port is capable of accepting both HDMI and

MHL electrical signals. Automatic detection between HDMI

and MHL is achieved by using cable impedance detection

through the CD_SENSE pin.

Both MHL and HDMI interfaces of the ADV7480 allow

authentication of a video receiver, decryption of encoded data at

the receiver, and renewability of that authentication during

transmission, as specified by the HDCP 1.4 protocol.

Dual extended display identification data (EDID) support is

provided via an on-chip 512-byte EDID RAM. The EDID RAM

must be programmed at power-up. It can be configured as two

256-byte EDIDs for dual mode operation (one 256-byte EDID

for the HDMI receiver, and one 256-byte EDID for the MHL

receiver), or as a single 512-byte EDID for single mode operation.

The ADV7480 has a synchronization regeneration block used to

regenerate the data enable (DE) signal based on the measurement

of the video format being displayed and to filter the horizontal

and vertical synchronization signals to prevent glitches.

The combined HDMI/MHL receiver also supports TMDS error

reduction coding, 4-bit (TERC4) error detection, used for the

detection of corrupted HDMI or MHL packets.

•

HDMI RECEIVER

The HDMI receiver supports video formats ranging from 480i

to 1080p, and display resolutions from VGA (640 × 480 at

60 Hz) to UXGA (1600 × 1200 at 60 Hz).

The HDMI receiver allows programmable equalization of the

HDMI data signals. This equalization compensates for the high

frequency losses inherent in HDMI and DVI cabling, especially

at longer lengths and higher frequencies. The receiver is capable

of equalizing for cable lengths up to 30 meters to achieve robust

receiver performance.

The main HDMI receiver features include

•

162.0 MHz (UXGA at 24 BPP) maximum TMDS clock

frequency.

Integrated fully adaptive equalizer for cable lengths up to

30 meters.

HDCP 1.4 support.

Internal HDCP keys.

HDCP repeater support, up to 25 key selection vectors

(KSVs) supported.

PCM audio packet support.

Support for 8-channel TDM output data up to 48 kHz.

Repeater support.

Internal EDID RAM (512-byte for single mode, and

256-byte for dual mode operation).

Hot Plug assert output pin (HPD/CBUS).

CEC controller.

MHL RECEIVER

The MHL receiver supports video formats ranging from 480i to

720p/1080i, and display resolutions from VGA (640 × 480 at

60 Hz) to XGA (1024 × 768 at 60 Hz).

The MHL receiver allows programmable equalization of the

MHL data signals. This equalization compensates for the high

frequency losses inherent in MHL cabling, especially at longer

lengths and higher frequencies. The receiver is capable of

equalizing for cable lengths of up to 2 meters to achieve robust

receiver performance.

The MHL receiver includes the following pins:

• RX0N and RX0P. In MHL mode, this differential pair

receives the data transmitted as a differential signal, and

the clock transmitted on the common mode.

HPD/CBUS. In MHL mode, this pin is used for CBUS

communication.

VBUS_EN. This pin provides an enable signal for an

external source providing 5 V of power to the MHL source

on VBUS.

RX_5V/VBUS. In MHL mode, this pin is an input

monitoring the VBUS signal provided by an external

source enabled by VBUS_EN.

CD_SENSE. This pin detects whether the signals provided

to the HDMI/MHL receiver are HDMI signals or MHL

signals. A high level indicates MHL, and a low level

indicates HDMI.

•

Rev. 0 | Page 17 of 19

ADV7480

Data Sheet

The audio is output on a single flexible serial digital audio

output port supporting I2S-compatible, left justified and right

justified audio output modes in master mode only. TDM is also

supported, allowing up to eight audio channels with a sample

rate up to 48 kHz to be transmitted over the single serial digital

audio interface.

COMPONENT PROCESSOR

The ADV7480 has one any-to-any 3 × 3 CSC matrix. The CSC

block is located in the processing path before the CP section.

CSC enables YCbCr-to-RGB and RGB-to-YCbCr conversions.

Many other standards of color space can be implemented using

the color space converter.

CP features include

• Support for all video modes supported by the HDMI/MHL

receiver. These include 525i, 625i, 525p, 625p, 1080i, 1080p,

and display resolutions from VGA (640 × 480 at 60 Hz) to

UXGA (1600 × 1200 at 60 Hz).

Manual adjustments including gain (contrast), offset

(brightness), hue, and saturation.

Free run output mode that provides stable timing when no

video input is present.

Timing adjustments controls for HS/VS/DE timing.

MIPI CSI-2 TRANSMITTER

The ADV7480 features one MIPI CSI-2 transmitter

(Transmitter A).

The four-lane transmitter consists of four differential data lanes

(DA0N, DA0P, DA1N, DA1P, DA2N, DA2P, DA3N and DA3P),

and a differential clock lane (CLKAN and CLKAP). It supports

four data lanes, two data lanes and one data lane muxing

options, and can be used to transmit video received on either

the HDMI/MHL receiver (processed through the CP) or the

8-bit digital input port.

The main features of the 4-lane MIPI transmitter

(Transmitter A) include

•

Support for 8-bit and 10-bit YCbCr 4:2:2 video modes.

Support for 24-bit RGB 4:4:4 (RGB888), 18-bit RGB 4:4:4

(RGB666), and 16-bit RGB 4:4:4 (RGB565) video modes.

Support for video formats ranging from 480i to 1080p, and

display resolutions from VGA to UXGA (certain

restrictions apply to the muxing option, video mode, and

video format that can be selected).

Data lanes and clock lane remapping to ease PCB layout.

•

8-BIT DIGITAL INPUT/OUTPUT PORT

The ADV7480 features an 8-bit digital bidirectional port. The

following formats are supported both as input and output ports:

•

8-bit interleaved 4:2:2 SDR input/output with embedded

timing codes

8-bit interleaved 4:2:2 DDR input/output with embedded

timing codes

The maximum input and output video resolution supported is

720p/1080i in both SDR and DDR modes.

Video received on the 8-bit digital input port can be routed to

the four-lane MIPI CSI-2 transmitter. Video sent on the 8-bit

digital output port can be routed from the CP core.

•

INTERRUPTS

The ADV7480 features three interrupt request pins. INTRQ1

and INTRQ2 can be programmed to trigger interrupts based on

various selectable events related to the HDMI/MHL receiver

(video and audio related) and the CP. INTRQ3 is dedicated to

events related to the MHL CBUS.

AUDIO PROCESSING

The ADV7480 features an audio processor that handles the

audio extracted from the MHL or HDMI stream by the

HDMI/MHL receiver. It contains an audio mute controller that

can detect a variety of conditions that may result in audible

extraneous noise in the audio output. On detection of these

conditions, a 2-channel linear PCM audio signal can be ramped

down to a mute state to prevent audio clicks or pops.

Rev. 0 | Page 18 of 19

Data Sheet

OUTLINE DIMENSIONS

A1 BALL

CORNER

9.10

9.00 SQ

8.90

1098

ADV7480

A1 BALL

CORNER

7.20

BSC SQ

0.80

BSC

TOP VIEW

DETAIL A

0.90

REF

0.383

0.343

0.303

0.26

REF

BOTTOM VIEW

0.975

0.910

0.845

1.400

1.253

1.173

DETAIL A

SEATING

PLANE

0.50

0.45

0.40

BALL DIAMETER

COPLANARITY

0.12

COMPLIANTTO JEDEC STANDARDS MO-275-DDAB-1

WITH THE EXCEPTION TO PACKAGE HEIGHT

Figure 14. 100-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

(BC-100-4)

Dimensions shown in millimeters

ORDERING GUIDE

Model

1, 2, 3

ADV7480WBBCZ

ADV7480WBBCZ-RL

Temperature Range

−40°C to +85°C

Package Description

100-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

Package Option

BC-100-4

Z = RoHS Compliant Part.

W = Qualified for Automotive Applications.

This device is programmed with internal HDCP keys. Customer must have HDCP adopter status (consult Digital Protection, LLC, for licensing requirements) to

purchase any components with internal HDCP keys.

AUTOMOTIVE PRODUCTS

The ADV7480W models are available with controlled manufacturing to support the quality and reliability requirements of automotive

applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers

should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in

automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to

obtain the specific Automotive Reliability reports for these models.

C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

registered trademarks are the property of their respective owners.

D12045-0-6/14(0)

Rev. 0 | Page 19 of 19